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PDF ADATE318 Data sheet ( Hoja de datos )
| Número de pieza | ADATE318 | |
| Descripción | 600 MHz Dual Integrated DCL | |
| Fabricantes | Analog Devices | |
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600 MHz Dual Integrated DCL with PPMU, VHH Drive
Capability, Level Setting DACs, and On-Chip Calibration
Engine
ADATE318
FEATURES
600 MHz/1200 Mbps data rate
3-level driver with high-Z and reflection clamps
Window and differential comparators
±25 mA active load
Per pin PPMU with −2.0 V to +6.5 V range
Low leakage mode (typically 4 nA)
Integrated 16-bit DACs with offset and gain correction
High speed operating voltage range: –1.5 V to +6.5 V
Dedicated VHH output pin range: 0.0 V to 13.5 V
1.1 W power dissipation per channel
Driver
3-level voltage range: –1.5 V to +6.5 V
Precision trimmed output resistance
Unterminated swing: 200 mV minimum to 8 V maximum
725 ps minimum pulse width, VIH − VIL = 2.0 V
Comparator
Differential and single-ended window modes
>1.2 GHz input equivalent bandwidth
Load
±25 mA current range
Per pin PPMU (PPMU)
Force voltage/compliance range: –2.0 V to +6.5 V
5 current ranges: 40 mA, 1 mA, 100 μA, 10 μA, 2 μA
External sense input for system PMU
Go/no-go comparators
Levels
Fully integrated 16-bit DACs
On-chip gain and offset calibration registers and
add/multiply engine
Package
84-lead 10 mm × 10 mm LFCSP (0.4 mm pitch)
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
GENERAL DESCRIPTION
The ADATE318 is a complete, single-chip ATE solution that
performs the pin electronics functions of driver, comparator,
and active load (DCL), four quadrant, per pin, parametric
measurement unit (PPMU). It has VHH drive capability per
chip to support flash memory testing applications and integ-
rated 16-bit DACs with an on-chip calibration engine to
provide all necessary dc levels for operation of the part.
The driver features three active states: data high, data low, and
terminate mode, as well as a high impedance inhibit state. The
inhibit state, in conjunction with the integrated dynamic
clamps, facilitates the implementation of a high speed active
termination. The output voltage capability is −1.5 V to +6.5 V
to accommodate a wide range of ATE and instrumentation
applications.
The ADATE318 can be used as a dual, single-ended drive/
receive channel or as a single differential drive/receive channel.
Each channel of the ADATE318 features a high speed window
comparator as well as a programmable threshold differential
comparator for differential ATE applications. A four quadrant
PPMU is also provided per channel.
All dc levels for DCL and PPMU functions are generated by 24
on-chip 16-bit DACs. To facilitate accurate levels programming,
the ADATE318 contains an integrated calibration function to
correct gain and offset errors for each functional block.
Correction coefficients can be stored on chip, and any values
written to the DACs are automatically adjusted using the
appropriate correction factors.
The ADATE318 uses a serial programmable interface (SPI) bus
to program all functional blocks, DACs, and on-chip calibration
constants. It also has an on-chip temperature sensor and
over/undervoltage fault clamps for monitoring and reporting
the device temperature and any output pin or PPMU voltage
faults that may occur during operation.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
ADATE318
Parameter
TEMPERATURE MONITOR
Temperature Sensor Gain
Temperature Sensor Accuracy over
Temperature Range
VREF INPUT REFERENCE
DAC Reference Input Voltage Range
(VREF Pin)
Input Bias Current
DUTGND INPUT
Input Voltage Range,
Referenced to AGND
Input Bias Current
Test
Min Typ Max Unit Level Conditions
10 mV/K D
±6 K CT
4.950 5.000 5.050 V
D
−0.1
−100
100 μA P
+0.1 V
+100 μA
D
P
Provided externally:
VREF pin = +5.000 V
VREFGND pin = 0.000 V (not referenced to VDUTGND)
Tested with 5.000 V applied
Tested at −100 mV and +100 mV
Table 2. Driver (VIH − VIL ≥ 100 mV to Meet DC and AC Performance Specifications)
Parameter
Min Typ Max Unit
Test
Level
Conditions
DC SPECIFICATIONS
High-Speed Differential Input
Characteristics
High Speed Input Termination
Resistance: DATx, RCVx
92 100 108 Ω P Impedance between each pair of DATx and RCVx pins;
push 4 mA into positive pin, force 0.8 V on negative pin,
measure voltage between pins; calculate resistance (ΔV/ΔI)
Input Voltage Differential: DATx, RCVx 0.2
0.4 1.0 V
D 0.2 V < VDM < 1.0 V
Input Voltage Range: DATx, RCVx
0.0
3.3 V
D 0.0 V < (VCM ± VDM/2) < 3.3 V
Output Characteristics
Output High Range, VIH
−1.4
+6.5 V
D
Output Low Range, VIL
−1.5
+6.4 V
D
Output Term Range, VIT
−1.5
+6.5 V
D
Functional Amplitude
(VIH – VIL)
0.0 8.0
VD
DC Output Current Limit Source
75
130 mA
P
Drive high, VIH = +6.5 V, short DUTx pin to −1.5 V, measure
current
DC Output Current Limit Sink
−130
−75 mA
P
Drive low, VIL = −1.5 V, short DUTx pin to +6.5 V, measure
current
Output Resistance, ±40 mA
46
48.6 51
Ω
P
ΔVDUT/ΔIDUT; source: VIH = 3.0 V, IDUT = +1 mA, +40 mA;
sink: VIL = 0.0 V, IDUT = −1 mA, −40 mA
DC ACCURACY
VIH tests with VIL = −2.5 V, VIT = −2.5 V
VIL tests with VIH = +7.5 V, VIT = +7.5 V
VIT tests with VIL = −2.5 V, VIH = +7.5 V, unless otherwise
specified
VIH, VIL, VIT Offset Error
−500
+500 mV
P
Measured at DAC Code 0x4000 (0 V), uncalibrated
VIH, VIL, VIT Offset Tempco
±625
μV/°C CT
VIH, VIL, VIT Gain
1.0
1.1 V/V
P
Gain derived from measurements at DAC Code 0x4000
(0 V) and DAC Code 0xC000 (5 V); based on ideal DAC
transfer functions (see Table 21)
VIH, VIL, VIT Gain Tempco
±40 ppm/°C CT
VIH, VIL, VIT DNL
±1
mV CT
After two point gain/offset calibration; calibration points at
0x4000 (0 V) output; 0xC000 (+5 V) output; measured over
full specified output range
VIH, VIL, VIT INL
−7
+7 mV
P
After two point gain/offset calibration; applies to nominal
VDD = +10.0 V supply case only
Rev. 0 | Page 5 of 80
5 Page 
Parameter
Maximum Programmable
Hysteresis
Hysteresis Resolution
CMRR
DC PSRR
AC SPECIFICATIONS
Min
−1
Propagation Delay,
Input to Output
Propagation Delay Tempco
Propagation Delay Matching,
High Transition to Low
Transition
Propagation Delay Matching,
High to Low Comparator
Propagation Delay Change
(Dispersion) With Respect To
Slew Rate:
400 ps and 1 ns
(20% to 80%)
Overdrive:
250 mV and 750 mV
1 V Pulse Width:
0.7 ns, 1 ns, 5 ns, 10 ns
0.5 V Pulse Width:
0.6 ns, 1 ns, 5 ns, 10 ns
Duty Cycle:
5% to 95%
Minimum Detectable
Pulse Width
Input Equivalent Bandwidth,
Terminated
Comparator Pre-Emphasis (CLC)
CLC Amplitude Range
CLC Resolution
Pre-Emphasis Time Constant
Typ Max Unit
117 mV
5.6 mV
+1 mV/V
±5 mV/V
0.83 ns
2.6 ps/ºC
15 ps
17 ps
ADATE318
Test
Level
CB
Conditions
D Calculated over hystersis control Code 10 to Code 31
P Offset measured at VCM = −1.5 V and +6.5 V with VDM = 0.0 V,
offset error change
CT Measured at calibration points
All ac specifications performed after dc level calibration,
unless noted; input transition time ~200 ps, 20% to 80%,
measured with 50 Ω to external termination voltage (VTTC),
peaking set to CLC = 2, unless otherwise specified
CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for
other channel
CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for
other channel
CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for
other channel
CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term
mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for
other channel
31
32
+1/−
21
+1/−
31
18
0.5
1038
11
1.6
4.8
ps CB
ps CB
ps CB
ps CB
ps CB
ns CB
MHz
CB
% CB
% per bit
ns
CB
CB
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing; driver term
mode, VIT = 0.0 V; comparator threshold = 0.0 V, repeat for
other channel
VDUT0 = 0.0 V; for 250 mV: VDUT1: 0 V to 0.5 V swing; for
750 mV: VDUT1: 0 V to 1.0 V swing; driver term mode,
VIT = 0.0 V; comparator threshold = −0.25 V; repeat for
other channel with comparator threshold = +0.25 V
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz;
driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V;
repeat for other channel
VDUT0 = 0.0 V; VDUT1: −0.25 V to +0.25 V swing at 32 MHz;
driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V;
repeat for other channel
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz;
driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V;
repeat for other channel
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz;
driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V;
greater than 50% output differential amplitude; repeat for
other channel
VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing; driver term
mode, VIT = 0.0 V; comparator threshold = 0.0 V, CLC = 2 as
measured by shmoo; repeat for other channel
VDUT0 = 0.0 V; VDUT1: −0.8 V to +0.8 V swing, driver term
mode, VIT = 0.0 V; comparator threshold = 0.0 V;
comparator CLC set to maximum; repeat for other channel
3-bit amplitude control
VDUT0 = 0.0 V; VDUT1: −0.8 V to +0.8 V swing, driver term
mode, VIT = 0.0 V; comparator threshold = 0.0 V;
comparator CLC set to maximum; repeat for other channel
Rev. 0 | Page 11 of 80
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADATE318.PDF ] | |
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