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PDF ADATE305 Data sheet ( Hoja de datos )
| Número de pieza | ADATE305 | |
| Descripción | 250 MHz Dual Integrated DCL | |
| Fabricantes | Analog Devices | |
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250 MHz Dual Integrated DCL with Level
Setting DACs, Per Pin PMU, and Per Chip VHH
ADATE305
FEATURES
Driver
3-level driver with high-Z mode and built-in clamps
Precision trimmed output resistance
Low leakage mode (typically <10 nA)
Voltage range: up to −2.0 V to +6.0 V
1.6 ns minimum pulse width, 2 V terminated
2.1 ns minimum pulse width, 3 V terminated
Comparator
Window and differential comparator
500 MHz input equivalent bandwidth
Load
±12 mA maximum current capability
Per pin PMU
Force voltage range: up to −2.0 V to +6.0 V
5 current ranges: 32 mA, 2 mA, 200 μA, 20 μA, 2 μA
Levels
14-bit DAC for DCL levels
Typically < ±5 mV INL (calibrated)
16-bit DAC for PMU levels
Typically < ±1.5 mV INL (calibrated) linearity in FV mode
HVOUT output buffer
0 V to 13.5 V output range
100-lead, 14 mm × 14 mm, TQFP_EP package
900 mW per channel with no load
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
GENERAL DESCRIPTION
The ADATE305 is a complete, single-chip solution that performs
the pin electronic functions of the driver, the comparator, and
the active load (DCL), per pin PMU, and dc levels for ATE appli-
cations. The device also contains an HVOUT driver with a VHH
buffer capable of generating up to 13.5 V.
The driver features three active states: data high mode, data low
mode, and term mode, as well as an inhibit state. The inhibit
state, in conjunction with the integrated dynamic clamp, facili-
tates the implementation of a high speed active termination.
The ADATE305 supports two output voltage ranges: −2.0 V
to +6.0 V and −1.5 V to +6.0 V by adjusting the positive and
negative supply voltages.
The ADATE305 can be used as either a dual single-ended drive/
receive channel or a single differential drive/receive channel.
Each channel of the ADATE305 features a high speed window
comparator per pin for functional testing, as well as a per pin
PMU with FV, or FI and MV, or MI functions. All necessary dc
levels for DCL functions are generated by on-chip 14-bit DACs.
The per pin PMU features an on-chip 16-bit DAC for high
accuracy and contains integrated range resistors to minimize
external component counts.
The ADATE305 uses a serial bus to program all functional blocks
and has an on-board temperature sensor for monitoring the
device temperature.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
ADATE305
DRIVER
VH − VL ≥ 200 mV (to meet dc/ac specifications).
Table 2.
Parameter
DC SPECIFICATIONS
High-Speed Differential Logic
Input Characteristics (DATA, RCV)
Input Termination Resistance
Input Voltage Differential
Common-Mode Voltage
Input Bias Current
Pin Output Characteristics
Output High Range, VH
Output Low Range, VL
Output Term Range, VT
Functional Amplitude (VH − VL)
DC Output Current Limit
Source
DC Output Current Limit Sink
Output Resistance, ±50 mA
ABSOLUTE ACCURACY
VH, VL, VT Uncalibrated Accuracy
VH, VL, VT Offset Tempco
VH, VL, VT DNL
VH, VL, VT INL
VH, VL, VT Resolution
DUTGND Voltage Accuracy
VH, VL, VT Crosstalk
Overall Voltage Accuracy
VH, VL, VT DC PSRR
AC SPECIFICATIONS
Rise/Fall Times
0.2 V Programmed Swing
1.0 V Programmed Swing
2.0 V Programmed Swing
3.0 V Programmed Swing
3.0 V Programmed Swing
5.0 V Programmed Swing
Rise to Fall Matching
Min
92
0.2
0.85
−20.0
−1.4
−1.5
−1.5
0.0
75
−120
45.0
−250
−10
−7
1000
Typ
100
+2.2
7.5
100
−100
47.0
±75
±450
±1
±2.5
0.6
±1.3
±2
±10
±15
1000
800
950
1175
1650
2350
30
Max
108
1.0
2.35
+20.0
+6.0
+5.9
+6.0
120
−75
49.0
+250
+10
+1
+7
1500
Unit
Ω
V
V
μA
V
V
V
V
mA
mA
Ω
mV
μV/°C
mV
mV
mV
mV
mV
mV
mV/V
ps
ps
ps
ps
ps
ps
ps
Test
Level
P
PF
PF
P
D
D
D
D
P
P
P
P
CT
CT
P
PF
P
CT
CT
CT
CB
CB
CB
P/CB
CB
CB
CB
Conditions/Comments
Push 6 mA into xP pins, force 1.3 V on xN pins; measure voltage
from xP to xN, calculate resistance (ΔV/ΔI)1
Each pin tested at 2.85 V and 0.35 V, while the other high speed
pin remains open
Amplitude can be programmed to VH = VL, accuracy specs
apply when VH − VL ≥ 200 mV
Driver high, VH = 6.0 V, short DUTx pin to −2.0 V, measure current
Driver low, VL = −1.5 V, short DUTx pin to 6.0 V, measure current
Source: driver high, VH = 3.0 V, IDUTx = 1 mA and 50 mA;
sink: driver low, VL = 0.0 V, IDUTx = −1 mA and −50 mA; ΔVDUT/ΔIDUT
VH tests done with VL = −2.5 V and VT= −2.5 V;
VL tests done with VH = 7.5 V and VT = 7.5 V;
VT tests done with VL = −2.5 V and VH = +7.5 V; unless otherwise
specified
Error measured at calibration points of 0 V and 5 V
Measured at calibration points
After two-point gain/offset calibration
After two-point gain/offset calibration; measured over driver
output ranges
After two-point gain/offset calibration; range/number of DAC
bits as measured at calibration points of 0 V and 5 V
Over ±0.1 V range; measured at end points of VH, VL, and VT
functional range
VL = −1.5 V: VH = −1.4 V → 6.0 V, VT = −1.5 V → 6.0 V;
VH = 6.0 V: VL = −1.5 V → 5.9 V, VT = −1.5 V → 6.0 V;
VT = 1.5 V: VL = −1.5 V → 5.9 V, VH = −1.4 V → 6.0 V; dc crosstalk
on VL, VH, VT output level when other driver DACs are varied
Sum of INL, crosstalk, DUTGND, and tempco over ±5°C, after
gain/offset calibration
Measured at calibration points
Toggle DATAxx
VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80%
VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 2.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90%
VH = 5.0V, VL = 0.0 V, unterminated; 10% to 90%
VH = 3.0 V, VL = 0.0 V, terminated; rise to fall within one channel
Rev. 0 | Page 5 of 56
5 Page 
ADATE305
ACTIVE LOAD
See Table 29 for load control information.
Table 6.
Parameter
DC SPECIFICATIONS
Input Characteristics
VCOM Voltage Range
VDUT Range
VCOM Accuracy, Uncalibrated
VCOM Resolution
VCOM DNL
VCOM INL
DUTGND Voltage Accuracy
Output Characteristics
IOL
Maximum Source Current
Uncalibrated Offset
Uncalibrated Gain
Resolution
DNL
INL
90% Commutation Voltage
IOH
Maximum Sink Current
Uncalibrated Offset
Uncalibrated Gain
Resolution
DNL
INL
90% Commutation Voltage
Output Current Tempco
Min
−1.25
−1.5
−200
−7
−7
12
−600.0
−12
−80
12
−600.0
−12
−80
Typ
±30
0.6
±1
±2
±1
±100
±4
1.5
±3.0
±20
±100
±4
1.5
±3.0
±20
±1.5
Max
+5.75
+6.0
+200
1
+7
+7
+600.0
+12
2
+80
0.25
+600.0
+12
2
+80
0.25
Unit
V
V
mV
mV
mV
mV
mV
mA
μA
%
μA
μA
μA
V
mA
μA
%
μA
μA
μA
V
μA/°C
Test
Level
D
D
P
PF
CT
P
P
D
P
P
PF
CT
P
P
D
P
P
PF
CT
P
P
CT
Conditions/Comments
Load active on, RCV active, unless otherwise noted
IOH = IOL = 6 mA, VCOM error measured at the calibration
points of 0.0 V and 5.0 V
IOH = IOL = 6 mA, after two-point gain/offset calibration;
range/number of DAC bits as measured at the calibration
points of 0.0 V and 5.0 V
IOH = IOL = 6 mA, after two-point gain/offset calibration
IOH = IOL = 6 mA, after two-point gain/offset calibration;
measured over VCOM range of −1.25 V to +5.75 V
Over ±0.1 V range; measured at end points of VCOM functional
range
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL offset calculated
from the calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL gain calculated from
the calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; range/number of DAC bits as measured at the
calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point
gain/offset calibration
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; measured over IOL range of 0 mA to 12 mA
IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL reference at
VDUTx = −1.0 V, measure IOL current at VDUTx = 1.75 V, ensure > 90%
of reference current
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH offset calculated
from the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH gain calculated from
the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration; range/number of DAC bits as measured
at the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/
offset calibration; measured over IOH range of 0 mA to 12 mA
IOH = IOL =12 mA, VCOM = 2.0 V, measure IOH reference at
VDUTx = 5.0 V, measure IOH current at VDUTx = 2.25 V, ensure >
90% of reference current
Measured at calibration points
Rev. 0 | Page 11 of 56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADATE305.PDF ] | |
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