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PDF AD9643 Data sheet ( Hoja de datos )
| Número de pieza | AD9643 | |
| Descripción | 1.8 V Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V
Dual Analog-to-Digital Converter (ADC)
AD9643
FEATURES
SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
−151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 785 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The AD9643 is a dual, 14-bit analog-to-digital converter (ADC)
with sampling speeds of up to 250 MSPS. The AD9643 is designed
to support communications applications, where low cost, small
size, wide bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC output data is routed directly to the two external
14-bit LVDS output ports and formatted as either interleaved or
channel multiplexed.
Flexible power-down options allow significant power savings,
when desired.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
VIN+A
VIN–A
VCM
VIN+B
VIN–B
PIPELINE
14-BIT 14
ADC
AD9643
PARALLEL
DDR LVDS
PIPELINE
14-BIT 14
ADC
AND
DRIVERS
REFERENCE
SERIAL PORT
1 TO 8
CLOCK
DIVIDER
D0±.
.
...
D13±
DCO±
OR±
OEB
PDWN
NOTES
SCLK SDIO CSB
CLK+ CLK– SYNC
1. THE D0± TO D13± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
Figure 1.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface.
The AD9643 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.
2. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating LVDS outputs.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
4. SYNC input allows synchronization of multiple devices.
5. 3-pin, 1.8 V SPI port for register programming and register
readback.
6. Pin compatibility with the AD9613, allowing a simple
migration down from 14 bits to 12 bits. This part is also pin
compatible with the AD6649 and the AD6643.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9643
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range,
duty cycle stabilizer (DCS) enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.75 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1
POWER CONSUMPTION
Sine Wave Input (DRVDD = 1.8 V)
Standby Power4
Power-Down Power
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9643-170
Min Typ Max
14
Guaranteed
±10
+2/−6
±0.75
±0.25
±1.8
±1.5
±13
±2.5/
+3.5
±5
±70
1.33
1.75
2.5
20
0.9
1.7 1.8 1.9
1.7 1.8 1.9
196 250
145 160
614
90
10
AD9643-210
Min Typ Max
14
Guaranteed
±10
+3/−5
±0.75
±0.25
±2
±1.5
±13
−2/
+3.5
±5
±80
1.33
1.75
2.5
20
0.9
1.7 1.8 1.9
1.7 1.8 1.9
217 265
160 185
680
90
10
AD9643-250
Min Typ Max
14
Guaranteed
±10
±4
±0.75
±0.25
±3.5
±1.5
±13
−2.5/
+3.5
±5
±100
1.33
1.75
2.5
20
0.9
1.7 1.8 1.9
1.7 1.8 1.9
256 275
180 210
785
90
10
1 Measured with a low input frequency, full-scale sine wave.
2 Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND).
Unit
Bits
mV
%FSR
LSB
LSB
LSB
LSB
mV
%FSR
ppm/°C
ppm/°C
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mW
mW
mW
Rev. E | Page 3 of 36
5 Page 
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Conditions
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
AD9643
Min Typ Max Unit
1 0.3
1 0.4
ns
ns
2 ns
2 ns
40 ns
2 ns
2 ns
10 ns
10 ns
10 ns
10 ns
Rev. E | Page 9 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9643.PDF ] | |
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