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PDF AD9480 Data sheet ( Hoja de datos )
| Número de pieza | AD9480 | |
| Descripción | 250 MSPS 3.3V A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
DNL = ± 0.25 LSB
INL = ± 0.26 LSB
Single 3.3 V supply operation (3.0 V to 3.6 V)
Power dissipation of 590 mW at 250 MSPS
1 V p-p analog input range
Internal 1.0 V reference
Single-ended or differential analog inputs
LVDS outputs (ANSI 644 levels)
Power-down mode
Clock duty-cycle stabilizer
APPLICATIONS
Digital oscilloscopes
Instrumentation and measurement
Communications
Point-to-point radios
Predistortion loops
GENERAL DESCRIPTION
The AD9480 is an 8-bit, monolithic analog-to-digital converter
(ADC) optimized for high speed and low power consumption.
Small in size and easy to use, the product operates at a
250 MSPS conversion rate, with excellent linearity and dynamic
performance over its full operating range.
To minimize system cost and power dissipation, the AD9480
includes an internal reference and track-and-hold circuit. The
user only provides a 3.3 V power supply and a differential
encode clock. No external reference or driver components are
required for many applications.
The digital outputs are LVDS (ANSI 644) compatible with an
option of twos complement or binary output format. The
output data bits are provided in parallel fashion along with an
LVDS output clock, which simplifies data capture.
Fabricated on an advanced BiCMOS process, the AD9480 is
available in a 44-lead surface-mount package (TQFP) specified
over the industrial temperature range −40°C to +85°C.
8-Bit, 250 MSPS
3.3 V A/D Converter
AD9480
FUNCTIONAL BLOCK DIAGRAM
VREF SENSE
AGND DrGND DRVDD AVDD
REFERENCE
AD9480
VIN+
VIN–
T&H
8-BIT
ADC
PIPELINE
CORE
8
16
LVDS
D7–D0
(LVDS)
CLK+
CLK–
CLOCK
MGMT
LOGIC
DCO+
DCO-
(LVDS)
PDWN
S1 LVDSBIAS
Figure 1.
PRODUCT HIGHLIGHTS
1. Superior linearity. A DNL of ±0.25 makes the AD9480
suitable for instrumentation and measurement
applications.
2. Power-down mode. A power-down function may be
exercised to bring total consumption down to 15 mW.
3. LVDS outputs (ANSI-644). LVDS outputs simplify timing
and improve noise performance
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
1 page  
AD9480
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and
clock inputs, unless otherwise noted.
Table 2.
Parameter
CLOCK INPUTS (CLK+, CLK−)
Differential Input
Common-Mode Voltage1
Input Resistance
Input Capacitance
LOGIC INPUTS (PDWN, S1) 2
PDWN Logic 1 Voltage
PDWN Logic 0 Voltage
PDWN Logic 1 Input Current
PDWN Logic 0 input Current
PDWN, S1 Input Resistance
PDWN, S1 Input Capacitance
DIGITAL OUTPUTS
Differential Output Voltage (VOD)3
Output Offset Voltage (VOS)
Output Coding
Temp
Full
Full
Full
25°C
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Test Level
IV
VI
VI
V
IV
IV
VI
VI
V
V
VI
VI
IV
AD9480-250
Min Typ Max
200
1.4 1.5 1.68
4.2 5.5 6.0
4
2.0
0.8
±160
10
30
4
247 454
1.125
1.375
Twos complement or binary
Unit
mV p-p
V
kΩ
pF
V
V
µA
µA
kΩ
pF
mV
V
1 The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V.
2 S1 is a multilevel logic input, see Table 8.
3 LVDSBIAS resistor = 3.74 kΩ.
Rev. A | Page 4 of 28
5 Page 
AD9480
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. It also may be
reported in dBc (that is, degrades as signal level is lowered) or
dBFS (that is, always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It also may be reported in
dBc (that is, degrades as signal level is lowered) or in dBFS (that
is, always relates back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic), reported in dBc.
Transient Response Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Rev. A | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD9480.PDF ] | |
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