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What is IDT72V3696?

This electronic component, produced by the manufacturer "Integrated Device Technology", performs the same function as "3.3 VOLT CMOS TRIPLE BUS SyncFIFO".


IDT72V3696 Datasheet PDF - Integrated Device Technology

Part Number IDT72V3696
Description 3.3 VOLT CMOS TRIPLE BUS SyncFIFO
Manufacturers Integrated Device Technology　
Logo Integrated Device Technology Logo　


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3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING
16,384 x 36 x 2
32,768 x 36 x 2
65,536 x 36 x 2
IDT72V3686
IDT72V3696
IDT72V36106
FEATURES
• Memory storage capacity:
IDT72V3686 – 16,384 x 36 x 2
IDT72V3696 – 32,768 x 36 x 2
IDT72V36106 – 65,536 x 36 x 2
• Clock frequencies up to 100 MHz (6.5ns access time)
• Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
• Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1024)
• Serial or parallel programming of partial flags
• Big- or Little-Endian format for word and byte bus sizes
• Loopback mode on Port A
• Retransmit Capability
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
• Pin compatible to the lower density parts, IDT72V3626/72V3636/
72V3646/72V3656/72V3666/72V3676
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
LOOP
MRS1
PRS1
FFA/IRA
AFA
FS2
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
RT1
RTM
RT2
36
FIFO1 and
FIFO2
Retransmit
Logic
MBF2
Mail 1
Register
36
RAM ARRAY
16,384 x 36
36
32,768 x 36
65,536 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
16
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM ARRAY
36 16,384 x 36
32,768 x 36
65,536 x 36
36
Mail 2
Register
MBF1
18
B0-B17
Port-B
Control
Logic
CLKB
RENB
CSB
MBB
SIZEB
Common
Port
Control
Logic
(B and C)
EFB/ORB
AEB
BE
FWFT
FFC/IRC
AFC
FIFO2,
Mail2
Reset
Logic
18
Port-C
Control
Logic
MRS2
PRS2
C0-C17
CLKC
WENC
MBC
SIZEC
4676 drw01
www.DataSheet4U.netIDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFOis a trademark of Integrated Device Technology, Inc.
COMMERICAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-4676/4

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IDT72V3696 equivalent
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFOTM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O
Description
FS0/SD FlagOffsetSelect0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,
Serial Data
FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three Offset register
programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024),
FS1/SEN FlagOffsetSelect1/ I parallel load from Port A, and serial load.
FS2(1)
Serial Enable
When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to
FlagOffsetSelect2 I the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 56 for the
72V3686, 60 for the 72V3696, and 64 for the 72V36106. The first bit write stores the Y-register (Y1) MSB and
the last bit write stores the X-register (X2) LSB.
LOOP
Loopback Select
I This pin selects the loopback feature for Port A. During Loopback data from FIFO2 will be directed to the input of
FIFO1. to initiate a Loop the LOOP pin must be held LOW and the ENA pin must be HIGH.
MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
Select
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects
FIFO2 output-register data for output.
MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
Select
active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output
register data for output.
MBC
MBF1
MBF2
MRS1
MRS2
PRS1/
RT1
PRS2/
RT2
Port C Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
Master Reset
Master Reset
Partial Reset/
Retransmit FIFO1
Partial Reset/
Retransmit FIFO2
I A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
Master Reset.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or
parallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and
C for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while MRS1 is LOW.
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects
the programming method (serial or parallel) and one of the five flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.
I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read and write
pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read pointer only to
the first memory location.
I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read and write
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer only to
the first memory location.
RENB
RTM
Port B Read Enable I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
RetransmitMode I This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on FIFO1
or FIFO2 respectively.
5


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