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PDF IDT72V36104 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V36104 | |
| Descripción | 3.3 VOLT CMOS SyncBiFIFO | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING
16,384 x 36 x 2
IDT72V3684
32,768 x 36 x 2
IDT72V3694
65,536 x 36 x 2
IDT72V36104
FEATURES
• Memory storage capacity:
IDT72V3684 – 16,384 x 36 x 2
IDT72V3694 – 32,768 x 36 x 2
IDT72V36104 – 65,536 x 36 x 2
• Clock frequencies up to 100 MHz (6.5ns access time)
• Two independent clocked FIFOs buffering data in opposite
directions
• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has five
default offsets (8, 16, 64, 256 and 1,024 )
• Serial or parallel programming of partial flags
• Retransmit Capability
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
• Auto power down minimizes power dissipation
• Available in space saving 128-pin Thin Quad Flatpack (TQFP)
• Pin compatible to the lower density parts, IDT72V3624/72V3634/
72V3644/72V3654/72V3664/72V3674
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
FFA/IRA
AFA
FS2
FS0/SD
FS1/SEN
A0-A35
EFA/ORA
AEA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
36
RT1
RTM
RT2
36
FIFO1 and
FIFO2
Retransmit
Logic
Mail 1
Register
36
RAM ARRAY
16,384 x 36
36
32,768 x 36
65,536 x 36
FIFO1
Write
Pointer
Read
Pointer
Status Flag
Logic
Programmable Flag
Offset Registers
Timing
Mode
16
FIFO2
Status Flag
Logic
Read
Pointer
Write
Pointer
RAM ARRAY
36 16,384 x 36
32,768 x 36
65,536 x 36
36
MBF2
Mail 2
Register
www.DataSheet4U.netIDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MBF1
36
EFB/ORB
AEB
36
FIFO2,
Mail2
Reset
Logic
4677 drw01
Port-B
Control
Logic
FWFT
B0-B35
FFB/IRB
AFB
MRS2
PRS2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
NOVEMBER 2003
DSC-4677/5
1 page  
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O
Description
FS0/SD FlagOffsetSelect0/ I FS1/SENand FS0/SD are dual-purpose inputs used for flag offset register programming. During Master
Serial Data
Reset, FS1/SENand FS0/SD, together with FS2, select the flag offset programming method. Three offset
register programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or
1,024), parallel load from Port A, and serial load.
FS1/SEN FlagOffsetSelect1/ I
Serial Enable,
When serial load is selected for flag offset register programming, FS1/SENis used as an enable
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SENis LOW, a rising edge on CLKA load
FS2(1) FlagOffsetSelect2 I the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset
registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write
stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB.
MBA Port A Mailbox
Select
I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level
selects FIFO2 output register data for output.
MBB Port B Mailbox
Select
I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO1 output register data for output.
MBF1 Mail1Register
Flag
MBF2 Mail2Register
Flag
O MBF1is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
O MBF2is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2
register are inhibited while MBF2is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1 FIFO1 Master
Reset
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port
Boutputregistertoallzeroes. ALOW-to-HIGHtransitiononMRS1selectstheprogrammingmethod(serialorparallel)
and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and
endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1is LOW.
MRS2 FIFO2 Master
Reset
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition onMRS2, toggled simultaneously with MRS1, selects the
programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-to-
HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW.
PRS1/ PartialReset/
RT1 RetransmitFIFO1
I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.
If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read
and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable
flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read
pointer only to the first memory location.
PRS2/ PartialReset/
RT2 RetransmitFIFO2
I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.
If RTMis in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read
and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag
settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer
only to the first memory location.
RTM RetransmitMode
I This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on
FIFO1 or FIFO2 respectively.
SIZE(1) Bus Size Select
I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH
selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port
B. The level of SIZE must be static throughout device operation
W/RA Port-AWrite/
Read Select
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RAis HIGH.
W/RB Port-BWrite/
Read Select
I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
NOTE:
1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or VCC.
5
5 Page 
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
COMMERCIALTEMPERATURERANGE
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFT inputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and
CLKB (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB)
to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed
by performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT input to choose
the desired timing mode must remain staticthroughoutFIFOoperation.Refer
to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Four registers in the IDT72V3684/72V3694/72V36104 are used to hold the
offset values for the Almost-Empty and Almost-Full flags. The Port B Almost-
Empty flag (AEB) Offset register is labeled X1 and the Port A Almost-Empty flag
(AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA) Offset
register is labeled Y1 and the Port B Almost-Full flag (AFB) Offset register is
labeled Y2. The index of each register name corresponds to its FIFO number.
The offset registers can be loaded with preset values during the reset of a FIFO,
programmed in parallel using the FIFO’s Port A data inputs, or programmed
in serial using the Serial Data (SD) input (see Table 1).
FS0/SD, FS1/SEN and FS2 function the same way in both IDT Standard
and FWFT modes.
— PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with
one of the five preset values listed in Table 1, the flag select inputs must be HIGH
or LOW during a master reset. For example, to load the preset value of 64 into
X1 and Y1, FS0, FS1 and FS2 must be HIGH when FlFO1 reset (MRS1) returns
HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the
preset values in the same way with FIFO2 Master Reset (MRS2), toggled
simultaneously with FIFO1 Master Reset (MRS1). For relevant preset value
loading timing diagram, see Figure 3.
— PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with FS2 HIGH or LOW, FS0 and FS1
LOW during the LOW-to-HIGH transition of MRS1 and MRS2. The state of FS2
at this point of reset will determine whether the parallel programming method
has Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag
Programming Flag Offset setup . It is important to note that once parallel
programming has been selected during a Master Reset by holding both FS0
& FS1 LOW, these inputs must remain LOW during all subsequent FIFO
operation. They can only be toggled HIGH when future Master Resets are
performed and other programming methods are desired.
After this reset is complete, the first four writes to FIFO1 do not store data in
RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non-
Interspersed Parity mode the Port A data inputs used by the Offset registers are
(A13-A0), (A14-A0), or (A15-A0) for the IDT72V3684, IDT72V3694, or
IDT72V36104, respectively. For Interspersed Parity mode the Port A data
inputs used by the Offset registers are (A14-A9, A7-A0), (A15-A9, A7-A0), or
(A16-A9, A7-A0) for the IDT72V3684, IDT72V3694, or IDT72V36104,
respectively. Thehighestnumberedinputisusedasthemostsignificantbitof
the binary number in each case. Valid programming values for the registers
range from 1 to 16,380 for the IDT72V3684; 1 to 32,764 for the IDT72V3694;
and 1 to 65,532 for the IDT72V36104. After all the offset registers are
TABLE 1 — FLAG PROGRAMMING
FS2 FS1/SEN FS0/SD MRS1 MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H H H ↑X
64
X
H H H X↑
X
64
H H L ↑X
H H L X↑
16
X
X
16
H L H ↑X
8
X
H L H X↑
X
8
L H H ↑X
L H H X↑
256
X
X
256
L L H ↑X
1,024
X
L L H X↑
X
1,024
L H L ↑↑
Serial programming via SD
H
LL
↑↑
Parallel programming via Port A(3,5)
L L L ↑↑
IP Mode(4, 5)
Serial programming via SD
Parallel programming via Port A(3,5)
IP Mode(4, 5)
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT72V36104.PDF ] | |
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