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PDF YSS932 Data sheet ( Hoja de datos )
| Número de pieza | YSS932 | |
| Descripción | 96kHz DIR Dolby Digital / Pro Logic II / DTS decoder Sub DSP | |
| Fabricantes | YAMAHA CORPORATION | |
| Logotipo |  |
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YSS932
AC3D3B
96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP
OUTLINE
YSS932 is one chip LSI consisting of three built-in blocks : SPDIF receiver (DIR), Dolby Digital (AC-3) /
Pro Logic II & DTS decoder (Main DSP) and programmable sound fields processing DSP (Sub DSP).
The Sub DSP is capable of realizing various sound fields, such as virtual surround by down-loading the
program and coefficient from outside.
FEATURES
[ DIR Block ]
• Sampling frequency: Two ranges are available including;
32k to 48kHz (normal rate) and 64k to 96kHz (double rate).
• Provides master clock, 256fs, to DAC, ADC and the other peripheral devices. The clock output can be
controlled with various modes determined by register settings.
• Has a pin that indicates the double rate operation.
• Every channel status and user data can be read through the microprocessor interface.
• Has an output pin for interrupt that is activated by changing of the status information.
• Internal operation frequency: 25MHz
[ Main DSP Block ]
• Dolby Digital (AC-3) / Pro Logic II and DTS decode.
• High quality internal 24 bit DSP.
• No external memory is required. (Memory for the center and surround channel signal delay is included.)
• AC-3 Karaoke mode.
• Supports compression mode at AC-3 / DTS decoding.
• Included de-emphasis filter for the PCM signal.
• Pro Logic II decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM signal.
• Reads Dolby Digital / DTS decode information through the microprocessor interface.
• Internal operation frequency: 30MHz
YAMAHA CORPORATION
www.DataSheet4U.com
YSS932 CATALOG
CATALOG No.: LSI-4SS932A2
2003.2
1 page  
YSS932
PIN FUNCTION
No. Name I/O
Function
1 TESTXI I LSI Test pin (must be connected to VSS)
2 TESTXO O LSI Test pin (to be open)
3 VDD2
- +2.5V power supply (for internal core logic)
4 XO
O Crystal oscillator connection
5 XI
I Crystal oscillator connection (24.576MHz)
6 TESTMS I+ LSI Test pin (to be open)
7 TESTXEN I+ LSI Test pin (to be open)
8 IPORT0 I+ General purpose input port
9 IPORT1 I+ General purpose input port
10 IPORT2 I+ General purpose input port
11 IPORT3 I+ General purpose input port
12 IPORT4 I+ General purpose input port
13 DDIN0 Is DIR: Digital audio interface data input 0
14 DDIN1 Is DIR: Digital audio interface data input 1 / General purpose input port
15 DDIN2 Is DIR: Digital audio interface data input 2 / General purpose input port
16 DDIN3 Is DIR: Digital audio interface data input 3 / General purpose input port
17 VSS
- Ground
18 CPO
A PLL filter connection
19 AVDD
- +3.3V power supply (for DIR block)
20 DIRPCO A DIR: PLL filter connection
21 DIRPRO A DIR: PLL filter connection
22 AVSS
- Ground (for DIR block)
23 TESTBRK I+ LSI Test pin (to be open)
24 TESTR1 I+ Initial Clear input for PLL in DSP block
25 TESTR2 I+ LSI Test pin (to be open)
26 VDD1
- +3.3V power supply (for I/O)
27 SDWCKI0 I+ Word clock input for SDIA, SDOA, SDIB, SDOB
28 SDBCKI0 I+ Bit clock input for SDIA, SDOA, SDIB, SDOB
29 /SDBCKO O Reverse clock output of DIRBCK or SDBCKI0
30 SDIA
I Input of bitstream or PCM data to Main DSP
31 SDOA2 O PCM data output from Main DSP (C, LFE)
32 SDOA1 O PCM data output from Main DSP (LS, RS)
33 SDOA0 O PCM data output from Main DSP (L, R)
34 SDIB3 I+ PCM data input 3 to Sub DSP
35 SDIB2 I+ PCM data input 2 to Sub DSP
36 SDIB1 I+ PCM data input 1 to Sub DSP
37 SDIB0 I+ PCM data input 0 to Sub DSP
38 VSS
- Ground
39 VDD2
- +2.5V power supply (for internal core logic)
40 DIRSDO O Output of bitstream or PCM data from DIR
41 DIRWCK O DIR: Serial data word clock (fs) output
42 DIRBCK O DIR: Serial data bit clock (64fs) output
43 DIRMCK O DIR: Serial data master clock (256fs or 128fs) output
44 ERR/BS O DIR: Data error detect / Block start output
45 SYNC/U O DIR: Serial data synchronized timing / User data output
46 FS128/C O DIR: Serial data master clock 128fs / Channel status output
47 DBL/V O DIR: Double rate lock detect / Validity flag output
48 SDWCKI1 I+ Word clock input for SDIB, SDOB
49 SDBCKI1 I+ Bit clock input for SDIB, SDOB
50 VSS
- Ground
51 SDOB3 O PCM data output from Sub DSP
52 SDOB2 O PCM data output from Sub DSP
53 SDOB1 O PCM data output from Sub DSP
54 SDOB0 O PCM data output from Sub DSP
55 VDD1
- +3.3v power supply (for I/O)
5
5 Page 
YSS932
/LOCK, ERR, DIRINT
The same data as LOCKN, DIRERR, DIRINT of DIR STATUS Register are output from /LOCK, ERR/BS,
DIRINT pins respectively.
The DIRERR data is output from ERR/BS pin at BSMOD=0 setting.
DBL
The information, whether the DDIN input signal is a double rate signal, is output from the DBL/V pin at
VMOD=0 setting.
If PLL in the DIR block is locked at double rate and the free-run mode is not used, "H" level is output.
If PLL in the DIR block is locked at normal rate or the free-run mode is used, "L" level is output.
1-5) Analog circuit for PLL in DIR block
DIRPCO, DIRPRO
These are capacitor and resistor connection pins for PLL in DIR block. As shown below, connect a 4700pF
capacitor and an 8.2kΩ resistor between DIRPCO and AVSS as close as physically possible to DIRPCO and
a 5.1kΩ resistor between DIRPRO and AVSS as close as physically possible to DIRPRO.
8.2kΩ
4700pF
5.1kΩ
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet YSS932.PDF ] | |
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