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2N3958 fiches techniques PDF

Micross - Low Noise

Numéro de référence 2N3958
Description Low Noise
Fabricant Micross 
Logo Micross 





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2N3958 fiche technique
2N3958
MONOLITHIC DUAL
N-CHANNEL JFET
The 2N3958 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
The 2N3958 family are matched JFET pairs for
differential amplifiers. The 2N3958 family of general
purpose JFETs is characterized for low and medium
frequency differential amplifiers requiring low offset
voltage, drift, noise and capacitance
FEATURES 
LOW DRIFT 
LOW LEAKAGE 
LOW NOISE 
ABSOLUTE MAXIMUM RATINGS  
|∆ VGS12 /T|= 5µV/°C max.
IG = 20pA TYP. 
en = 10nV/Hz TYP. 
The 2N3958 family also exhibits low capacitance - 6pF
max and a spot noise figure of -0.5dB max. The part
offers a superior tracking ability.
@ 25°C (unless otherwise noted) 
Maximum Temperatures 
Storage Temperature 
65°C to +200°C 
The hermetically sealed TO-71 and TO-78 packages
are well suited for high reliability and harsh environment
applications.
(See Packaging Information).
Operating Junction Temperature 
+150°C 
Maximum Voltage and Current for Each Transistor  Note 1 
VGSS 
Gate Voltage to Drain or Source 
VDSO 
Drain to Source Voltage 
IG(f)  Gate Forward Current 
Maximum Power Dissipation 
60V 
60V 
50mA 
Device Dissipation @ Free Air  Total                 400mW @ 25°C 
2N3958 Applications:
 
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
ƒ Wideband Differential Amps
ƒ High Input Impedance Amplifiers
SYMBOL 
| V GS12 / T| max. 
| V GS12 | max. 
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
CHARACTERISTICS 
DRIFT VS. 
TEMPERATURE 
OFFSET VOLTAGE 
VALUE  UNITS 
100  µV/°C 
25  mV 
CONDITIONS 
VDG=20V, ID=200µA 
TA=55°C to +125°C 
VDG=20V, ID=200µA 
SYMBOL 
CHARACTERISTICS 
MIN. 
TYP.  MAX. 
UNITS 
CONDITIONS 
BVGSS 
Breakdown Voltage 
60 
BVGGO 
GateToGate Breakdown 
60 
 
TRANSCONDUCTANCE 
 
YfSS 
Full Conduction 
1000 
YfS 
|YFS12 / Y FS| 
 
IDSS 
Click|IDSS12 / IDSS| 
Typical Operation 
Mismatch 
DRAIN CURRENT 
Full Conduction 
Mismatch at Full Conduction 
500 
‐‐ 
 
0.5 
‐‐ 
 
GATE VOLTAGE 
 
VGS(off) or Vp 
Pinchoff voltage 
1 
VGS(on) 
Operating Range 
0.5 
 
GATE CURRENT 
 
‐‐  ‐‐ 
V 
VDS = 0                  ID=1µA 
‐‐  ‐‐ 
V        I G= 1nA               ID= 0               IS= 0 
  
 
 
2000  3000 
µmho 
VDG= 20V         VGS= 0V      f = 1kHz 
To Buy700  1000 
0.6  3 
  
2  5 
1  5 
µmho 
% 
 
mA 
% 
     VDG= 20V         ID= 200µA     
 
 
VDG= 20V              VGS= 0V 
 
  
 
 
2  4.5 
V 
VDS= 20V               ID= 1nA 
‐‐  4 
V                VDS=20V                 ID=200µA 
  
 
 
IG 
IG 
IG 
IGSS 
 
YOSS 
YOS 
|YOS12| 
 
Operating 
High Temperature 
Reduced  VDG 
At Full Conduction 
OUTPUT CONDUCTANCE 
Full Conduction 
Operating 
Differential 
COMMON MODE REJECTION 
‐‐ 
‐‐ 
‐‐ 
‐‐ 
 
‐‐ 
‐‐ 
‐‐ 
 
20 
‐‐ 
5 
‐‐ 
 
‐‐ 
0.1 
0.01 
 
50 
50 
‐‐ 
100 
 
5 
1 
0.1 
 
pA 
nA 
pA 
pA 
 
µmho 
µmho 
µmho 
 
VDG= 20V          ID= 200µA 
TA= +125°C
 
VDG= 10V         ID= 200µA 
VDG= 20V              VDS= 0 
 
VDG= 20V              VGS= 0V 
VDG=  20V           ID= 200µA 
 
CMR 
20 log | VGS12/ VDS| 
‐‐  100  ‐‐ 
dB 
VDS = 10 to 20V        ID=200µA 
CMR 
20 log | VGS12/ VDS| 
‐‐  75  ‐‐ 
dB 
VDS = 5 to 10V        ID=200µA 
 
NOISE 
    
  VDS= 20V      VGS= 0V       RG= 10MΩ 
NF 
Figure 
‐‐  ‐‐  0.5 
dB 
f= 100Hz           NBW= 6Hz 
en 
Voltage 
‐‐ 
‐‐  15 
nV/Hz 
VDS=20V   ID=200µA   f=10Hz  NBW=1Hz 
 
CAPACITANCE 
    
 
 
CISS  Input  ‐‐  ‐‐  6  pF  VDS= 20V       VGS= 0V       f= 1MHz 
CRSS 
Reverse Transfer 
‐‐  ‐‐  2 
pF 
CDD 
DraintoDrain 
‐‐  0.1  ‐‐ 
pF 
VDG=  20V           ID= 200µA 
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
TO-71 / TO-78 (Bottom View)
Micross Components Europe
Available Packages:
2N3958 in TO-71 / TO-78
2N3958 available as bare die
Please contact Micross for full package and die dimensions
Tel: +44 1603 788967
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.

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