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PDF HDD16M72D9RPW Data sheet ( Hoja de datos )
| Número de pieza | HDD16M72D9RPW | |
| Descripción | DDR SDRAM Module 128Mbyte | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HDD16M72D9RPW
DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks
4K Ref., 184Pin-DIMM with PLL & Register Part No. HDD16M72D9RPW
GENERAL DESCRIPTION
The HDD16M72D9RPW is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory
module. The module consists of nine CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and
2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM. The HDD16M72D9RPW is a DIMM(Dual in line Memory
Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
• Part Identification
HDD16M72D9RPW – 10A : 100MHz (CL=2)
HDD16M72D9RPW – 13A : 133MHz (CL=2)
HDD16M72D9RPW – 13B : 133MHz (CL=2.5)
• Power supply : VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Selfwww.DataSheet4U.net refresh, 15.6us refresh interval (4K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1200 mil, double sided component
URL : www.hbe.co.kr
REV 1.0 (November.2002)
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
ABSOLUTE MAXIMUM RATINGS
HDD16M72D9RPW
PARAMETER
SYMBOL
RATING
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 3.6
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD 8.0
Short circuit current
IOS 50
Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
UNTE
V
V
V
°C
W
mA
POWER & DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) )
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Supply Voltage
VDD 2.3 2.7 V
I/O Supply Voltage
VDDQ 2.3 2.7 V
I/O Reference Voltage
I/O Termination Voltage(system)
VREF
VTT
VDDQ/2-50mV
VREF – 0.04
VDDQ/2+50mV
VREF + 0.04
V
V
1
2
Input High Voltage
VIH (DC)
VREF + 0.15
VREF + 0.3
V
Input Low Voltage
VIL (DC)
-0.3 VREF - 0.15 V
Input Voltage Level, CK and /CK inputs
VIN (DC)
-0.3 VDDQ + 0.3 V
Input Differential Voltage, CK and /CK inputs
VID (DC)
0.3 VDDQ + 0.6
V
Input leakage current
I LI -2
2 uA 3
Output leakage current
I OZ -5
5 uA
Output High current (VOUT = 1.95V)
I OH -16.8
mA
Output Low current (VOUT = 0.35V)
I OL 16.8
mA
Output High Current(Half strengh driver)
IOH -9
mA
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Output High Current(Half strengh driver)
IOL 9
mA
Notes
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
URL : www.hbe.co.kr
REV 1.0 (November.2002)
5 HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HDD16M72D9RPW.PDF ] | |
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