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PDF HDD16M64D8W Data sheet ( Hoja de datos )
| Número de pieza | HDD16M64D8W | |
| Descripción | DDR SDRAM Module 128Mbyte | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HDD16M64D8W
DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks,
4K Ref., DIMM,
Part No. HDD16M64D8W
GENERAL DESCRIPTION
The HANBiT HDD16M64D8W is 16M bit x 64 Double Data Rate SDRAM high density memory modules. The HANBiT
HDD16M64D8W consists of eight CMOS 16M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages
mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel
for each DDR SDRAM. The HDD16M64D8W is Dual In-line Memory Modules and intended for mounting into 184pin edge
connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are
possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device
to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURES
• Part Identification
HDD16M64D8W – 10A : 100MHz (CL=2)
HDD16M64D8W – 13A : 133MHz (CL=2)
HDD16M64D8W – 13B : 133MHz (CL=2.5)
• Power supply : VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presencewww.DataSheet4U.net detect with EEPROM
• PCB : Height 1250 mil, double sided component
URL : www.hbe.co.kr
REV 2.0 (November.2002)
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
DDR SDRAM IDD SPEC TABLE
HDD16M64D8W
SYMBOL
B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) UNIT NOTE
IDD0
840
760
760 mA
IDD1
1040
960
960 mA
IDD2P
28
24
24 mA
IDD2F
200
176
176 mA
IDD2Q
144
120
120 mA
IDD3P
280
280
280 mA
IDD3N
440
440
440 mA
IDD4R
1280
1136
1136
mA
IDD4W
1216
1040
1040
mA
IDD5
1480
1480
1480
mA
Normal
16
16
16 mA
IDD6
Low power
8
8
8 mA Optional
IDD7A
2640
2400
2400
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading cap.
AC OPERATING CONDITIONS
PARAMETER/ CONDITION
STMBOL
MIN
MAX
UNIT NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH (AC) VREF + 0.31
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL (AC)
VREF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
VID (AC)
0.7
VDDQ+0.6 V 1
Input Crossing Point Voltage, CK and CK inputs
VIX (AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V IX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation.
the AC and DC input specificatims are refation to a VREF envelope that has been bandwidth limited 20MHz.
www.DataSheet4U.net
AC OPERATING TEST CONDITIONS
PARAMETER
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
VALUE
0.5 * VDDQ
1.5
0.5
VREF+0.31/VREF-0.31
VREF
VTT
See Load Circuit
UNIT
V
V
V/ns
V
V
V
V
NOTE
URL : www.hbe.co.kr
REV 2.0 (November.2002)
5 HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HDD16M64D8W.PDF ] | |
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