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PDF HDD128M72D18RPW Data sheet ( Hoja de datos )
| Número de pieza | HDD128M72D18RPW | |
| Descripción | DDR SDRAM Module 1024Mbyte | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HDD128M72D18RPW
DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks,
8K Ref., 184Pin-DIMM with PLL & Register
Part No. HDD128M72D18RPW
GENERAL DESCRIPTION
The HDD128M72D18RPW is a 128M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory
module. The module consists of eighteen CMOS 64M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages
and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each DDR SDRAM. The HDD128M72D18RPW is a DIMM( Dual in line Memory
Module) .Synchronous design allows precise cycle c ontrol with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance mem ory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
• Part Identification
HDD128M72D18RPW – 13A : 133MHz (CL=2)
HDD128M72D18RPW – 13B : 133MHz (CL=2.5)
HDD128M72D18RPW – 16B : 166MHz (CL=2.5)
• 1024MB(64Mx72) Registered DDR DIMM based on 64Mx8 DDR SDRAM
• 2.5V ± 0.2V VDD and VDDQ power supply
• Auto & self refresh capability (8K Cycles / 64ms)
• All input and output are compatible with SSTL_2 interface
• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
• MRS cycle with address key programs
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- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Data scramble : Sequential & Interleave
• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
• The used device is 16M x 8bit x 4Banks DDR SDRAM
URL : www.hbe.co.kr
REV 1.0 (January. 2005)
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HDD128M72D18RPW
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 3.6
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD 1.5 * # of component
Short circuit current
IOS 50
Notes: Operation at above absolute maximum rating can adversely affect device reliability
UNTE
V
V
V
°C
W
mA
DC operating conditions
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) )
PARAMETER
SYMBOL
MIN
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage(system)
Input High Voltage
Input Low Voltage
Input Voltage Level, CK and /CK inputs
Input Differential Voltage, CK and /CK inputs
Input leakage current
Output leakage current
Output High current (Normal strength driver)
; VOUT=VTT + 0.84V
Output Low current (Normal strength driver)
; VOUT=VTT - 0.84V
Output High current (Half strength driver)
; VOUT=VTT + 0.45V
VDD
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
VID (DC)
I LI
I OZ
I OH
I OL
I OH
2.3
2.3
0.49*VDDQ
VREF – 0.04
VREF + 0.15
-0.3
-0.3
0.3
-2
-5
-16.8
16.8
-9
MAX
2.7
2.7
0.51*VDDQ
VREF + 0.04
VREF + 0.3
VREF - 0.15
VDDQ + 0.3
VDDQ + 0.6
2
5
UNIT
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
NOTE
1
2
3
Notes :
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth
limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which
may result
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in
VREF
noise.
VREF
should
be
de-coupled
with
an
inductance
of
≤
3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The
AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
URL : www.hbe.co.kr
REV 1.0 (January. 2005)
5 HANBit Electronics Co.,Ltd.
5 Page 
HANBit
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
HDD128M72D18RPW
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and
only one output switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire
temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown
drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
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as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables
3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the
lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table
given, this would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the
lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew
rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotony.
URL : www.hbe.co.kr
REV 1.0 (January. 2005)
11 HANBit Electronics Co.,Ltd.
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HDD128M72D18RPW.PDF ] | |
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