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PDF SE7210TP1-E Data sheet ( Hoja de datos )
| Número de pieza | SE7210TP1-E | |
| Descripción | Server Board Technical Product Specification | |
| Fabricantes | Intel Corporation | |
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Intel® Server Board
SE7210TP1-E
Technical Product Specification
www.DataSheet4U.com
Intel order number C49240-002
Revision 2.0
October 2004
Enterprise Platforms and Services Marketing
1 page  
Intel® Server Board SE7210TP1-E TPS
Table of Contents
Table of Contents
1. Introduction .......................................................................................................................... 1
1.1 Chapter Outline........................................................................................................ 1
1.2 Server Board Use Disclaimer .................................................................................. 2
2. Server Board Overview ........................................................................................................ 3
2.1 SE7210TP1-E SKU Availability ............................................................................... 3
2.2 SE7210TP1-E Feature Set ...................................................................................... 3
3. Functional Architecture ....................................................................................................... 7
3.1 Processor Subsystem.............................................................................................. 7
3.1.1 Reset Configuration Logic ....................................................................................... 8
3.1.2 Processor Support ................................................................................................... 8
3.1.3 Microcode ................................................................................................................ 9
3.1.4 Processor Cache ..................................................................................................... 9
3.1.5 Hyper-Threading Technology .................................................................................. 9
3.2 Intel E7210 Chipset ................................................................................................. 9
3.2.1 Intel 827210 Memory Controller Hub (MCH) ........................................................... 9
3.2.2 Intel 82802AC 8 Megabit Firmware Hub (FWH) .................................................... 10
3.2.3 PCI-X ..................................................................................................................... 10
3.2.4 Low Profile Riser Slot ............................................................................................ 10
3.2.5 SMBus Interface .................................................................................................... 11
3.2.6 6300ESB I/O Controller Hub.................................................................................. 11
3.2.7 PCI Interface.......................................................................................................... 11
3.2.8 IDE Interface.......................................................................................................... 12
3.2.9 Serial ATA (SATA) Controller ................................................................................ 12
3.2.10 Low Pin Count (LPC) Interface .............................................................................. 13
3.2.11 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) ..... 13
3.2.12 Advanced Programmable Interrupt Controller (APIC)............................................ 13
3.2.13 Universal Serial Bus (USB) Controller ................................................................... 13
3.2.14 Real Time Clock, CMOS SRAM, and Battery ........................................................ 14
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3.2.15 GPIO...................................................................................................................... 15
3.2.16 Enhanced Power Management ............................................................................. 15
3.2.17 System Management Bus (SMBus 2.0)................................................................. 15
3.3 Memory Subsystem ............................................................................................... 15
Revision 2.0
v
5 Page 
Intel® Server Board SE7210TP1-E TPS
List of Tables
List of Tables
Table 1. Processor Support Matrix ............................................................................................... 8
Table 2. Supported Memory Configurations ............................................................................... 16
Table 3. Supported System Bus Frequency and Memory Speed Combinations ........................ 16
Table 4. Characteristics of Dual/Single Channel Configuration with/without Dynamic Mode ..... 17
Table 5: PCI Bus Segment Characteristics................................................................................. 22
Table 6. DMA Channels.............................................................................................................. 24
Table 7. Interrupts....................................................................................................................... 24
Table 8. PCI Interrupt Routing Map ............................................................................................ 25
Table 9: Video Modes ................................................................................................................. 32
Table 10. 10/100 Ethernet LAN Connector LEDs ....................................................................... 34
Table 11. 10/100/1000 LAN Connector LED States ................................................................... 34
Table 12. System Memory Map .................................................................................................. 36
Table 13. PCI Configuration Space Map .................................................................................... 37
Table 14. I/O Map ....................................................................................................................... 37
Table 15. PCI Bus Configuration IDs .......................................................................................... 39
Table 16: Supported BIOS Features........................................................................................... 40
Table 17: BIOS Setup Keyboard Command Bar Options ........................................................... 48
Table 18: BIOS Setup Main Menu Options ................................................................................. 50
Table 19. Advanced Menu .......................................................................................................... 50
Table 20. CPU Configuration Submenu...................................................................................... 51
Table 21. IDE Configuration Submenu ....................................................................................... 52
Table 22. Primary/Secondary/Third/Fourth Master/Slave Submenu........................................... 53
Table 23. Primary/Secondary/Third/Fourth Master/Slave Submenu........................................... 54
Table 24. Primary/Secondary/Third/Fourth Master/Slave Submenu........................................... 54
Table 25. Primary/Secondary/Third/Fourth Master/Slave Submenu........................................... 55
Table 26. Primary/Secondary/Third/Fourth Master/Slave Submenu........................................... 55
Table 27. Floppy Configuration Submenu .................................................................................. 56
Table 28. Super I/O Configuration Submenu.............................................................................. 57
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Table 29. USB Configuration Submenu...................................................................................... 58
Table 30. USB Mass Storage Device Configuration Sub-menu Selections ................................ 58
Table 31. PCI Configuration Submenu ....................................................................................... 59
Table 32. Boot Features ............................................................................................................. 60
Revision 2.0
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