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PDF FAN7190 Data sheet ( Hoja de datos )
| Número de pieza | FAN7190 | |
| Descripción | Gate-Drive IC | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FAN7190_F085
High-Current, High & Low-Side, Gate-Drive IC
May 2010
Features
Floating Channels for Bootstrap Operation to +600V
Typically 4.5A/4.5A Sourcing/Sinking Current Driving
Capability
Common-Mode dv/dt Noise Canceling Circuit
Built-in Under-Voltage Lockout for Both Channels
Matched Propagation Delay for Both Channels
3.3V and 5V Input Logic Compatible
Output In-phase with Input
Applications
Diesel and gasoline Injectors/Valves
MOSFET-and IGBT high side driver applications
Description
The FAN7190_F085 is a monolithic high- and low-side
gate-drive IC, which can drive high speed MOSFETs and
IGBTs that operate up to +600V. It has a buffered output
stage with all NMOS transistors designed for high pulse
current driving capability and minimum cross-conduction.
Fairchild’s high-voltage process and common-mode
noise canceling techniques provide stable operation of
the high-side driver under high dv/dt noise circumstances.
An advanced level shift circuit offers high-side gate driver
operation up to VS=-9.8V (typical) for VBS=15V.
The UVLO circuit prevents malfunction when VDD and
VBS are lower than the specified threshold voltage.
The high current and low output voltage drop feature
make this device suitable for magnetic- and piezo type
injectors and general MOSFET/IGBT based high side
driver applications.
8-SOP
Ordering Information
Part Number
FAN7190M
FAN7190MX
Package
8-SOP
Operating
Temperature Range
-40C ~ 125C
Eco Status
RoHS
Packing Method
Tube
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
www.DataSheet4U.com
© 2010 Fairchild Semiconductor Corporation
FAN7190_F085 Rev. 1.0.0
www.fairchildsemi.com
1 page  
Electrical Characteristics
VBIAS (VDD, VBS)=15.0V, VS=COM, -40C <=TA<= 125C, unless otherwise specified. The VIL, VIH, and IIN parameters
are referenced to COM and are applicable to the respective input signals HIN and LIN. The VO and IO parameters are
referenced to COM and VS is applicable to the respective output signals HO and LO.
Symbol
Characteristics
Test Condition
Min. Typ. Max. Unit
POWER SUPPLY SECTION (VDD AND VBS)
VDDUV+ VDD and VBS Supply Under-Voltage
VBSUV+ Positive-going Threshold
VDDUV- VDD and VBS Supply Under-Voltage
VBSUV- Negative-going Threshold
VDDUVH VDD and VBS Supply Under-Voltage
VBSUVH Lockout Hysteresis Voltage
ILK Offset Supply Leakage Current
IQBS Quiescent VBS Supply Current
IQDD Quiescent VDD Supply Current
IPBS Operating VBS Supply Current
IPDD Operating VDD Supply Current
LOGIC INPUT SECTION (HIN, LIN)
VIH Logic "1" Input Voltage
VIL Logic "0" Input Voltage
IIN+ Logic "1" Input Bias Current
IIN- Logic "0" Input Bias Current
RIN Input Pull-down Resistance
GATE DRIVER OUTPUT SECTION (HO, LO)
VOH High-level Output Voltage, VBIAS-VO
VOL Low-level Output Voltage, VO
IO+
Output High, Short-circuit Pulsed
Current(4)
IO-
RoutH
RoutL
VS
Output Low, Short-circuit Pulsed
Current(4)
Output driver impedance(4)
Output driver impedance(4)
Allowable Negative VS Pin Voltage for
HIN Signal Propagation to HO
VB=VS=600V
VIN=0V or 5V
VIN=0V or 5V
fIN=20kHz, rms value
fIN=20kHz, rms value
7.8 8.8 9.8
7.2 8.3 9.1 V
0.5
50
45 110 µA
75 150
530 700
µA
530 750
VIN=5V
VIN=0V
2.5
V
1.2
25 50
µA
1.0 2.0
100 200
K
No Load
No Load
VO=0V, VIN=5V with PW<10µs
VO=15V, VIN=0V with
PW<10µs
VO=3.0V, IO, source=250mA
VO=2.0V, IO, sink=250mA
3.5
3.5
1.5 V
35 mV
4.5
A
4.5
12
8
-9.8 -7.0 V
Note:
4. This parameter guaranteed by design.
Dynamic Electrical Characteristics
VBIAS (VDD, VBS)=15.0V, VS=COM=0V, CL=1000pF and -40C <=TA<= 125C unless otherwise specified.
Symbol
Characteristics
Test Condition
Min. Typ. Max.
ton Turn-on Propagation Delay
toff Turn-off Propagation Delay
www.DataShMeTet4U.cDoemlay Matching, HS & LS Turn-on/off
tr Turn-on Rise Time
tf Turn-off Fall Time
VS=0V
VS=0V
140 200
140 200
0 50
25 50
20 45
Unit
ns
© 2010 Fairchild Semiconductor Corporation
FAN7190_F085 Rev. 1.0.0
5
www.fairchildsemi.com
5 Page 
Physical Dimensions
.
6.20
5.80
5.00
4.80
3.81
8
A
5
B
4.00
3.80
1.75
0.65
5.60
PIN ONE
INDICATOR
(0.33)
1
4
1.27
0.25 M C B A
1.27
LAND PATTERN RECOMMENDATION
0.25
0.10
1.75 MAX
R0.10
R0.10
8°
0°
0.90
0.406
C
0.51
0.33
0.10 C
0.50
0.25
x
45°
GAGE PLANE
0.36
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
SEE DETAIL A
0.25
0.19
OPTION A - BEVEL EDGE
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
Figure 24. 8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
www.DastpaeSchifeiceat4llyUt.hceomwarranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FAN7190_F085 Rev. 1.0.0
11
www.fairchildsemi.com
11 Page | ||
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| PDF Descargar | [ Datasheet FAN7190.PDF ] | |
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