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PDF FAN6204 Data sheet ( Hoja de datos )
| Número de pieza | FAN6204 | |
| Descripción | Synchronous Rectification Controller | |
| Fabricantes | Fairchild Semiconductor | |
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November 2010
FAN6204
Synchronous Rectification Controller for Flyback
and Forward Freewheeling Rectification
Features
SR Controller
Suited for Flyback Converter in QR, DCM, and
CCM Operation
Suited for Forward Freewheeling Rectification
Internal Green Mode for Lower No-Load Power
Consumption and Higher Light-Load Efficiency
PWM Frequency Tracking with Secondary-Side
Winding Voltage Detection
Ultra-Low VDD Operating Voltage for Various Output
Voltage Applications (5V~24V)
Ultra-Low Green Mode Operating Current:
1.1mA Typical
VDD Pin Over-Voltage Protection (OVP)
12V (Typical) Gate Driver Clamp
8-Pin SOP Package
Applications
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Description
FAN6204 is a secondary-side synchronous rectification
(SR) controller to drive SR MOSFET for improving
efficiency. The IC is suitable for flyback converters and
forward free-wheeling rectification.
FAN6204 can be applied in continuous or discontinuous
conduction mode (CCM and DCM) and quasi-resonant
(QR) flyback converters based on the proprietary
innovative linear-predict timing-control technique. The
benefits of this technique include a simple control
method without current-sense circuitry to accomplish
noise immunity.
With PWM frequency tracking and secondary-side
winding voltage detection, FAN6204 can operate in both
fixed- and variable-frequency systems.
In Green Mode, the SR controller stops all SR switching
operation to reduce the operating current. Power
consumption is maintained at minimum level in light-
load condition.
Ordering Information
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Part Number
FAN6204MY
Operating
Temperature Range
-40°C to +105°C
Package
8-Pin, Small Outline Package (SOP)
Packing Method
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6204 • Rev. 1.0.0
www.fairchildsemi.com
1 page  
Electrical Characteristics
Unless otherwise specified, VDD=4.5V~25V and TA=-40°C ~ 105°C.
Symbol
Parameter
Conditions
VOP Continuously Operating Voltage
VDD-ON
VDD-OFF
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
IDD-OP Operating Current
IDD-GREEN Operating Current in Green Mode
IDD-ST Startup Current
VDD-OVP VDD Over-Voltage Protection
VDD-OVP-HYST Hysteresis Voltage for VDD OVP
tVDD-OVP VDD OVP Debounce Time
VDD=15V, LPC=50KHz, MOSFET
CISS=6000pF
VDD=15V
VDD< VDD-ON
Output Driver Section
VZ Gate Output Clamp Voltage
VOL Output Voltage Low
VOH Output Voltage High
tR Rising Time
tF Falling Time
tPD_HIGH_LPC
Propagation Delay to OUT HIGH
(LPC Trigger)
VDD=6V, IO=50mA
VDD=6V, IO=50mA
VDD=12V, CL=6nF, OUT=2V~9V
VDD=6V, CL=6nF, OUT=0.4V~4V
VDD=12V, CL=6nF, OUT=9V~2V
VDD=6V, CL=6nF, OUT=4V~0.4V
tR: 0V~2V, VDD = 12V
tPD_LOW_LPC
Propagation Delay to OUT LOW
(LPC Trigger)(3)
tF: 100%~90%, VDD = 12V
tMAX-PERIOD
VPMOS-ON
VPMOS-ON-
HYS
tINHIBIT
VGATE-PULL-
HIGH
Limitation between LPC Rising Edge to Gate Falling Edge
Internal PMOS Turn-On to Pull-HIGH Gate(3)
Hysteresis Voltage On(3)
Gate Inhibit Time
M2 Option (Enable)
Gate Pull-HIGH Voltage
VDD = 5V
LPC Section
tBNK Blanking Time for Charging CT
tDELAY-COMP Sampling Continuous Time for tBNK Compensation(3)
VLPC-SOURCE LPC Lower Clamp Voltage
Source ILPC=5µA
ILPC-SOURCE LPC Source Current
VLPC=0V
www.DataShVeeLtP4CU-EN.comSR Enabled Threshold Voltage
VLPC-EN = VLPC-HIGH x 0.83 at VLPC-
HIGH x 0.83< 2V, VO=15V, VO=VDD,
VLPC-HIGH = 1.2V
VEN-CLAMP
SR Enable Threshold Clamp
Voltage
VLPC-EN =2V at VLPC-HIGH x 0.83 >
2V
VLPC-TH-HIGH
Threshold Voltage on LPC Rising
Edge
0.05Vo+0.05, VO=15V, VO=VDD
tBNK-DIS
Blanking Time LPC is HIGH
During SR Gate Turn-On Period
Prevent LPC Spike to Turn-Off
Gate
Min.
VDD-
OFF
4.3
4.0
Typ.
4.8
4.5
Max.
28.5
5.3
5.0
Unit
V
V
V
7 8 mA
1.1 1.3 mA
150 200 μA
26 27.5 28.5 V
1.8 2.1 2.4
V
40 70 100 μs
10 12 14 V
0.5 V
4V
30 70 120 ns
70 120 170 ns
20 50 100 ns
20 90 130 ns
250 ns
180
22.5 25.0 28.0
8.3
0.9
1.6 2.2 2.8
4.5
ns
μs
V
V
μs
V
400 500 600
1
0.1 0.2 0.3
40 80 120
ns
μs
V
μA
0.85 1.00 1.15 V
2
0.7 0.8 0.9
350
V
V
ns
© 2010 Fairchild Semiconductor Corporation
FAN6204 • Rev. 1.0.0
5
www.fairchildsemi.com
5 Page 
SR Gate
Normal Mode
3 Times
4.8µs
IM
4.8µs
Green Mode
4.8µs
periods (tS-PWM) is tracked for causal function, the
accuracy of switching period is important. Therefore, if
the detected switching period has a serious variation
under some abnormal conditions, the SR gate should
be terminated to prevent fault trigger.
Figure 20. Entering Green Mode
Figure 23. Fault Causal Timing Protection
Gate Expand Limit Protection
Gate expand limit protection controls on-time expansion
of the SR MOSFET. Once the discharge time of the
internal timing capacitor (tDIS.CT) is longer than 115% of
previous on time of the SR MOSFET (ton-SR(n-1));
ton-SR(n) is limited to 115% of ton-SR(n-1), as shown in
Figure 24. When output load changes rapidly from light
load to heavy load, voltage-second balance theorem
may not be applied. In this transient state, gate expand
limit protection is activated to prevent overlap between
SR gate and PWM gate.
Figure 21. Resuming Normal Operation
Causal Function
Causal function is utilized to limit the time interval (tSR-
MAX) from the rising edge of VLPC to the falling edge of
the SR gate. tSR-MAX is limited to 97% of previous
switching period, as shown in Figure 22. When the
system operates at fixed frequency, whether voltage-
second balance theorem can be applied or not, causal
function can guarantee reliable operation.
Figure 24. Gate Expand Limit Protection
RES Dropping Protection
RES dropping protection prevents VRES dropping too
much within a cycle. The VRES is sampled as a
reference voltage, VRES’, on VLPC rising edge. Once VRES
drops below 90% of VRES’ for longer than a debounce
time (tRES-DROP), the SR gate is turned off immediately,
as shown in Figure 25. When output voltage drops
rapidly within a switching cycle, voltage-second balance
may not be applied, RES dropping protection is
activated to prevent overlap.
Figure 22. Causal Function Operation
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Fault Causal Timing Protection
Fault causal timing protection is utilized to disable the
SR gate under some abnormal conditions. Once the
switching period (tS-PWM(n)) is longer than 120% of
previous switching period (tS-PWM(n-1)), SR gate is
disabled and enters Green Mode, as shown in Figure
23. Since the rising edge of VLPC among switching
© 2010 Fairchild Semiconductor Corporation
FAN6204 • Rev. 1.0.0
11
Figure 25. VRES Dropping Protection
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet FAN6204.PDF ] | |
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