B9949 Datasheet PDF - Cypress Semiconductor
| Part Number | B9949 | |
| Description | 1:15 Clock Distribution Buffer | |
| Manufacturers | Cypress Semiconductor | |
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B9949
3.3V 160-MHz 1:15 Clock Distribution Buffer
Features
• 160MHz Clock Support
• LVPECL or LVCMOS/LVTTL Clock Input
• LVCMOS/LVTTL Compatible Inputs
• 15 Clock Outputs: Drive up to 30 Clock Lines
• 1X and 1/2X Configurable Outputs
• Output Three-state Control
• 350 ps Maximum Output-to-Output Skew
• Pin Compatible with MPC949
• Industrial Temp. Range: –40°C to +85°C
• 52-Pin TQFP Package
Block Diagram
TCLK_SEL
TCLK0 (LVTTL)
TCLK1 (LVTTL)
0
1
PECL_CLK
PECL_CLK#
PCLK_SEL
DSELA
0
1
DSELB
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DSELC
DSELD
MR/OE#
Description
The B9949 is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL or LVC-
MOS/LVTTL compatible input clocks. These clock sources
can be used to provide for test clocks as well as the primary
system clocks. All other control inputs are LVCMOS/LVTTL
compatible. The 15 outputs are 3.3V LVCMOS or LVTTL com-
patible and can drive two series terminated 50Ω transmission
lines. With this capability the B9949 has an effective fan-out of
1:30.
The B9949 is capable of generating 1X and 1/2X signals from
a 1X source. These signals are generated and retimed inter-
nally to ensure minimal skew between the 1X and 1/2X sig-
nals. SEL(A:D) inputs allow flexibility in selecting the ratio of
1X to1/2X outputs.
The B9949 outputs can also be three-stated via MR/OE# in-
put. When MR/OE# is set HIGH, it resets the internal flip-flops
and three-states the outputs.
/1
/2
R
0
1
0
1
0
1
0
1
2 QA0:1
3 QB0:2
4
QC0:3
6 QD0:5
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07081 Rev. *C
Revised December 21, 2002
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B9949
AC Parameters[6]: VDDC = 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C
Parameter
Fmax
Tpd
FoutDC
Description
Maximum Input Frequency[7]
PECL_CLK to Q Delay[7]
TCLK to Q Delay[7]
Output Duty Cycle[7, 8]
Conditions
Measured at VDDC/2
Min.
160
4.0
4.2
TCYCLE/2
–1
Typ.
Max.
- 8.6
- 10.5
TCYCLE/2 +
1
tpZL, tpZH Output Enable Time (all outputs)
2 10
tpLZ, tpHZ
Tskew
Tskew (pp)
Output Disable Time (all outputs)
Output-to-Output Skew[7, 9]
Part-to-Part Skew [10]
Fin<130MHz
PECL_CLK to Q
2 10
350
1.5 2.75
TCLK to Q
2.0 4.0
Tr/Tf
Output Clocks Rise/Fall Time[9]
0.8V to 2.0V
0.10
1.0
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50Ω transmission lines.
8. 50% input duty cycle.
9. Outputs loaded with 30 pF each
10. Part-to-Part Skew at a given temperature and voltage
Unit
MHz
ns
ns
ns
ns
ps
ns
ns
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Document #: 38-07081 Rev. *C
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| Information | Total 8 Pages | |
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| Download | [ B9949.PDF Datasheet ] | |
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