|
|
PDF HY27UF084G2B Data sheet ( Hoja de datos )
| Número de pieza | HY27UF084G2B | |
| Descripción | 4Gbit (512Mx8bit) NAND Flash | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HY27UF084G2B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
1
HY27UF(08/16)4G2B Series
4Gbit (512Mx8bit) NAND Flash
4Gb NAND FLASH
HY27UF(08/16)4G2B
www.DataSheet4U.com
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.4 / Jan. 2008
1
1 page  
1
HY27UF(08/16)4G2B Series
4Gbit (512Mx8bit) NAND Flash
9&&
,2a,2
&(
,2a,2 [2QO\
:(
5( 5%
$/(
&/(
:3
966
Figure1: Logic Diagram
www.DataSheet4U.com
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Input / Outputs (x16 only)
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1: Signal Names
Rev 0.4 / Jan. 2008
5
5 Page 
1
HY27UF(08/16)4G2B Series
4Gbit (512Mx8bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
This operation is operated by writing 00h and 30h to the command register along with five address cycles.
Two types of operations are available: random read, serial page read. The random read mode is enabled when the
page address is changed. The 2112 bytes (x8) or 1056 words (x16) of data within the selected page are transferred to
the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by
analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in
25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device out-
put the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data
output command. Random data output can be operated multiple times regardless of how many times it is done in a
page.
3.2 Page Program.
The device is programmed by page. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 8 times. The addressing should be done on each pages
in a block. A page program cycle consists of a serial data loading period in which up to 2112bytes of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed
into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), fol-
lowed by the five cycle address inputs and then serial data. The bytes other than those to be programmed do not need
to be loaded. The device supports random data input in a page.
The column address of next data, which will be entered, may be changed to the address which follows random data
input command (85h). Random data input may be operated multiple times regardless of how many times it is done in
a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without pre-
viously entering the serial data will not initiate the programming process. The internal write state controller automati-
cally executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for
other tasks. Once the program process starts, the Read Status Register command may be entered to read the status
register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Sta-
tus bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming
is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write
verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the com-
mand register. Figure 14 details the sequence.
www.DataSheet4U.com
Rev 0.4 / Jan. 2008
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HY27UF084G2B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HY27UF084G2B | 4Gbit (512Mx8bit) NAND Flash | Hynix Semiconductor |
| HY27UF084G2M | 4Gbit (512K x 8-Bit) NAND Flash | Hynix Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |