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PDF K7B323635C Data sheet ( Hoja de datos )
| Número de pieza | K7B323635C | |
| Descripción | 1Mx36 & 2Mx18 Synchronous SRAM | |
| Fabricantes | Samsung semiconductor | |
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K7B323635C
K7B321835C
1Mx36 & 2Mx18 Synchronous SRAM
36Mb Sync. Burst SRAM Specification
100LQFP with Pb / Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
www.DataSheet4U.com
- 1 - Rev. 1.1 March 2008
1 page  
K7B323635C
K7B321835C
PIN CONFIGURATION(TOP VIEW)
1Mx36 & 2Mx18 Synchronous SRAM
DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
VDD
N.C.
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin LQFP
(20mm x 14mm)
K7B323635C (1Mx36)
80 DQPb
79 DQb7
78 DQb6
77 VDDQ
76 VSSQ
75 DQb5
74 DQb4
73 DQb3
72 DQb2
71 VSSQ
70 VDDQ
69 DQb1
68 DQb0
67 VSS
66 N.C.
65 VDD
64 ZZ
63 DQa7
62 DQa6
61 VDDQ
60 VSSQ
59 DQa5
58 DQa4
57 DQa3
56 DQa2
55 VSSQ
54 VDDQ
53 DQa1
52 DQa0
51 DQPa
PIN NAME
SYMBOL
PIN NAME
LQFP PIN NO.
SYMBOL
PIN NAME
LQFP PIN NO.
A0 - A19
Address Inputs
32,33,34,35,36,37,39 VDD
42,43,44,45,46,47,48, VSS
49,50,81,82,99,100
ADV
Burst Address Advance 83
N.C.
ADSP
Address Status Processor 84
ADSC
Address Status Controller 85
DQa0~a7
CLK Clock
89 DQb0~b7
CS1 Chip Select
98
DQc0~c7
CS2 Chip Select
97
DQd0~d7
CS2 Chip Select
92
DQPa~Pd
WEx(x=a,b,c,d) Byte Write Inputs
93,94,95,96
OE
Output Enable
86
GW
Global Write Enable
88
VDDQ
BW
Byte Write Enable
87
ZZ
Power Down Input
64
VSSQ
www.DataShLeBeOt4U.com Burst Mode Control
31
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
No Connect
14,16,38,66
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
Output Ground
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 5 - Rev. 1.1 March 2008
5 Page 
K7B323635C
K7B321835C
1Mx36 & 2Mx18 Synchronous SRAM
AC TIMING CHARACTERISTICS
PARAMETER
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (GW, BW, WEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
SYMBOL
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tCH
tCL
tAS
tSS
tDS
tWS
tADVS
tCSS
tAH
tSH
tDH
tWH
tADVH
tCSH
tPDS
tPUS
-75
MIN MAX
8.5 -
- 7.5
- 3.5
2.5 -
2.5 -
0-
- 3.5
- 4.0
2.5 -
2.5 -
2.0 -
2.0 -
2.0 -
2.0 -
2.0 -
2.0 -
0.5 -
0.5 -
0.5 -
0.5 -
0.5 -
0.5 -
2-
2-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
www.DataSheet4U.com
- 11 - Rev. 1.1 March 2008
11 Page | ||
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