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PDF K4S560432J Data sheet ( Hoja de datos )
| Número de pieza | K4S560432J | |
| Descripción | 256Mb J-die SDRAM Specification | |
| Fabricantes | Samsung semiconductor | |
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K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
256Mb J-die SDRAM Specification
54 TSOP-II
with Lead-Free & Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
www.Data1S.hFeoert4uUp.dcaotmes or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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K4S560432J
K4S560832J
K4S561632J
4.0 Package Physical Dimension
#54
#28
Synchronous DRAM
Unit : mm
#1
(1.50)
(R 0.15)
22.22 ± 0.10
(0.71)
0.80TYP
[0.80 ± 0.08]
Detail A
#27
(10°)
Detail B
(10°)
0.125
+0.075
- 0.035
0.10 MAX
[ 0.075 MAX
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
Detail A
Detail B
0.30
+0.10
- 0.05
0.35
+0.10
- 0.05
54Pin TSOP(II) Package Dimension
0.25TYP
(0° ∼ 8°)
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K4S560432J
K4S560832J
K4S561632J
13.0 AC Operating Test Conditions
Parameter
AC input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Output
870Ω
1200Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Synchronous DRAM
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Unit
V
V
ns
V
Z0 = 50Ω
VTT = 1.4V
50Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
14.0 Operating AC Parameter
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
CAS latency=3
CAS latency=2
50 (x16 only)
10
15
15
37.5
55
-
Version
60 (x16 only)
12
18
18
42
100
60
2
2 CLK + tRP
1
1
1
2
75
15
20
20
45
65
1
Unit Note
ns 1
ns 1
ns 1
ns 1
us
ns 1
CLK 2,5
-5
CLK 2
CLK 2
CLK 3
ea 4
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
www.Da5t.aSISnAhM1e0eSt04UMUNH.Gczormaencdombemloewnd1s00tMRDHLz=o2pCeLrKatainngdctoDnAdLit=io2nCsL, KtR+DtRL=P1. CLK and tDAL=1CLK + 20ns is also supported.
6. tRC =tRFC, tRDL = tWR.
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Rev. 1.22 August 2008
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| PDF Descargar | [ Datasheet K4S560432J.PDF ] | |
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