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PDF K24C04 Data sheet ( Hoja de datos )
| Número de pieza | K24C04 | |
| Descripción | (K24C02 - K24C16) EEPROM | |
| Fabricantes | K-Line | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de K24C04 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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Serial
EEPROM
K24C02 / K24C04 / K24C08 / K24C16
www.DataSheet4U.com
Spring 2008
1 page  
K24C02/K24C04/K24C08/K24C16
Two-wire Serial EEPROM
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods
will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see to Figure 2 on page 4).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 2 on page 4).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The K24C02/K24C04/K24C08/K24C16 features a low-power standby mode which is enabled: (a)
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by
following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Figure 1: Data Validity
SDA
SCL
Figure 2: Start and Stop Definition
DATA STABLE
DATA
CHANGE
DATA STABLE
www.DataShSeDetA4U.com
SCL
Spring 2008
START
STOP
V1.1 .004.
5 Page 
K24C02/K24C04/K24C08/K24C16
Two-wire Serial EEPROM
2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)
AC Electrical Characteristics
Applicable over recommended operating range from TA = -40。C to +85。C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
Parameter
Symbol
1.8-volt
5.0-volt
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Clock Frequency, SCL
fSCL
-
- 400 -
- 1000
kHz
Clock Pulse Width Low
tLOW
1.2 -
- 0.6
-
-
s
Clock Pulse Width High
tHIGH
0.6 -
- 0.4
-
-
s
Noise Suppression Time
tI
- - 50 - - 40
ns
Clock Low to Data Out Valid
tAA 0.05 - 0.9 0.05 - 0.55
s
Time the bus must be free before
a new transmission can start
tBUF
1.2 -
- 0.5
-
-
s
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
5.0V, 25。C, Byte Mode
tHD.STA 0.6 -
- 0.25
-
-
s
tSU.STA 0.6 -
- 0.25
-
-
s
tHD.DAT
0
-
-0
-
-
s
tSU.DAT
100
-
- 100 -
-
ns
tR - - 0.3 - - 0.3 s
tF
- - 300 -
- 100
ns
tSU.STO
0.6
-
- 0.25
-
-
s
tDH
50 -
- 50
-
-
ns
tWR - - 5 - - 5
ms
Endurance
1M
-
--
-
- Write Cycles
Note
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall time: 50 ns
Input and output timing reference voltages: 0.5 VCC
The value of RL should be concerned according to the actual loading
on the user's system.
www.DataSheet4U.com
Spring 2008
V1.1 .010.
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet K24C04.PDF ] | |
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