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PDF PCA9525 Data sheet ( Hoja de datos )
| Número de pieza | PCA9525 | |
| Descripción | Simple 2-wire bus buffer | |
| Fabricantes | NXP Semiconductors | |
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PCA9525
Simple 2-wire bus buffer
Rev. 1 — 25 February 2011
Product data sheet
1. General description
The PCA9525 is a monolithic CMOS integrated circuit for bus buffering in applications
including I2C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.
The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing
the maximum permissible bus capacitance on both sides of the buffer.
The PCA9525 includes a unidirectional buffer for the clock signal, and a bidirectional
buffer for the data signal. Slave devices which employ clock stretching are therefore not
supported.
In its most basic implementation, the buffer will allow an extended number of slave
devices to be attached to one (or more) master devices. In this case, all master devices
would be positioned on the Sxx_IN side of the PCA9525.
The direction pin (DIR) further enhances this function by allowing the unidirectional clock
signal to be reversed, thus allowing master devices on both sides of the buffer.
The enable (EN) function allows sections of the bus to be isolated. Individual parts of the
system can be brought on-line successively. This means a controlled start-up using a
diverse range of components, operating speeds and loads is easily achieved.
2. Features and benefits
Simple impedance isolating buffer for 2-wire buses
4 mA maximum static open-drain pull-down capability supports a wide range of bus
standards
Works with I2C-bus (Standard-mode, Fast-mode), SMBus (standard and high power
mode), and PMBus
Fast switching times allow operation in excess of 1 MHz
Enable allows bus segments to be disconnected
Hysteresis on inputs provides noise immunity
Operating voltages from 2.7 V to 5.5 V
Very low supply current
Uncomplicated characteristics suitable for quick implementation in most common
2-wire bus applications
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1 page  
NXP Semiconductors
PCA9525
Simple 2-wire bus buffer
8. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min Max Unit
VDD supply voltage
Vn voltage on any other pin
[1] −0.3
+7
V
[1] VSS − 0.5 VDD + 0.5 V
II/O
input/output current
any pin
- 20 mA
Ptot
Tstg
Tamb
total power dissipation
storage temperature
ambient temperature
operating
- 300 mW
−55
+125
°C
−40 +85 °C
[1] Voltages are specified with respect to pin 4 (VSS).
9. Characteristics
Table 4. Characteristics
Tamb = −40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max
Unit
Power supply
VDD supply voltage
operating
IDD supply current
quiescent; VDD = VI(EN) = 5.5 V
SCL_IN, SDA_IN = 800 kHz;
VDD = 5.5 V
Buffer ports (SDA_IN, SCL_IN, SDA_OUT, SCL_OUT)
2.7
-
[1] -
- 5.5
-1
170 -
V
μA
μA
VI2C-bus
VIL
I2C-bus voltage
LOW-level input voltage
VIH HIGH-level input voltage
VI(hys)
hysteresis of input voltage
ILI
IO(sink)
VOL
input leakage current
output sink current
LOW-level output voltage
Pins SDA_IN, SDA_OUT
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
VI2C-bus = VDD or GND
LOW-level; VI2C-bus < VIL
IOL = 4 mA
IOL = 100 μA
-
[2] -
[2] -
[2] 1.2
[2] 2.0
[2] 80
[2] 200
−1
4
-
-
-
-
-
-
-
-
-
-
-
80
3
VDD + 0.3
0.4
0.5
-
-
-
-
+1
-
300
-
V
V
V
V
V
mV
mV
μA
mA
mV
mV
Vlock
direction lock voltage
Vunlock
direction unlock voltage
www.DataSheet4U.com
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
[2] -
[2] -
[2] 2.0
[2] 4.8
-
-
-
-
1.3 V
3.0 V
-V
-V
PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
PCA9525
Simple 2-wire bus buffer
3.3 V
VDD
SCL
SDA
BUS MASTER
R1
1.1 kΩ
R2
1.1 kΩ
U3
MASTER/
SLAVE
U4
up to 400 pF load
(PCA9525)
or 4 nF load if only
PCA9605's used
(R1 and R2 = 110 Ω)
VDD
SCL_IN SCL_OUT
SDA_IN SDA_OUT
EN
PCA9525
DIR
U1
R3
1.1 kΩ
R4
1.1 kΩ
SLAVE
SLAVE
U5
up to 400 pF load (PCA9525)
U6
SCL
SDA
VDD
SCL_IN SCL_OUT
SDA_IN SDA_OUT
EN
PCA9605
DIR
U2
R5
110 Ω
R4
110 Ω
SCL
SDA
SLAVE
SLAVE
U7
up to 4 nF load (PCA9605)
U8
002aaf342
Fig 14. PCA9525 typical buffer application
Figure 15 shows the PCA9525 used with masters on both sides of the buffer. More than
one master may be used on the Sxx_IN side of the IC. However, to locate a master on the
Sxx_OUT side and have that master be able to communicate with devices on the Sxx_IN
side, it must either have direct control over the direction pin (DIR) of the PCA9525, or it
must request another controlling master to change the direction. In Figure 15, U4 uses an
IRQ to signal to U2 that is requests a direction change. Once in control, it could
alternatively use the bus to signal ‘release of control’.
www.DataSheet4U.com
PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet PCA9525.PDF ] | |
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