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PDF ADXRS453 Data sheet ( Hoja de datos )
| Número de pieza | ADXRS453 | |
| Descripción | High Performance / Digital Output Gyroscope | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Complete rate gyroscope on a single chip
±300°/sec angular rate sensing
Ultrahigh vibration rejection: 0.01°/sec/g
Excellent 16°/hour null bias stability
Internal temperature compensation
2000 g powered shock survivability
SPI digital output with 16-bit data-word
Low noise and low power
3.3 V to 5 V operation
−40°C to +105°C operation
Ultrasmall, light, and RoHS compliant
Two package options
Low cost SOIC_CAV package for yaw rate (z-axis) response
Innovative ceramic vertical mount package (LCC_V), which
can be oriented for pitch, roll, or yaw response
APPLICATIONS
Rotation sensing in high vibration environments
Rotation sensing for industrial and instrumentation
applications
High performance platform stabilization
High Performance,
Digital Output Gyroscope
ADXRS453
GENERAL DESCRIPTION
The ADXRS453 is an angular rate sensor (gyroscope) intended
for industrial, instrumentation, and stabilization applications in
high vibration environments. An advanced, differential, quad
sensor design rejects the influence of linear acceleration, enabling
the ADXRS453 to offer high accuracy rate sensing in harsh envi-
ronments where shock and vibration are present.
The ADXRS453 uses an internal, continuous self-test architec-
ture. The integrity of the electromechanical system is checked by
applying a high frequency electrostatic force to the sense structure
to generate a rate signal that can be differentiated from the base-
band rate data and internally analyzed.
The ADXRS453 is capable of sensing an angular rate of up to
±300°/sec. Angular rate data is presented as a 16-bit word that
is part of a 32-bit SPI message.
The ADXRS453 is available in a 16-lead plastic cavity SOIC
(SOIC_CAV) and an SMT-compatible vertical mount package
(LCC_V), and is capable of operating across a wide voltage
range (3.3 V to 5 V).
CP5
VX
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATION
HV DRIVE
CLOCK
PHASE- DIVIDER
LOCKED
LOOP AMPLITUDE
DETECT
BAND-PASS
FILTER
12-BIT
ADC
Z-AXIS ANGULAR
RATE SENSOR
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Q DAQ
P DAQ
ADXRS453
DEMOD
Q FILTER
SELF-TEST
CONTROL
ARITHMETIC
LOGIC UNIT
DECIMATION
FILTER
TEMPERATURE
CALIBRATION
FAULT
DETECTION
EEPROM
Figure 1.
LDO
REGULATOR
PDD
DVDD
AVDD
SPI
INTERFACE
MOSI
MISO
SCLK
CS
DVSS
PSS
AVSS
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DVDD 1
RSVD 2
16 SCLK
15 MOSI
RSVD 3
CS 4
MISO 5
ADXRS453
TOP VIEW
(Not to Scale)
14 AVDD
13 DVSS
12 RSVD
PDD 6
PSS 7
VX 8
11 AVSS
10 RSVD
9 CP5
Figure 3. Pin Configuration, 16-Lead SOIC_CAV
Table 4. Pin Function Descriptions, 16-Lead SOIC_CAV
Pin No.
Mnemonic
Description
1
DVDD
Digital Regulated Voltage. See Figure 26 for the application circuit diagram.
2
RSVD
Reserved. This pin must be connected to DVSS.
3
RSVD
Reserved. This pin must be connected to DVSS.
4 CS Chip Select.
5
MISO
Master In/Slave Out.
6 PDD Supply Voltage.
7 PSS Switching Regulator Ground.
8 VX High Voltage Switching Node. See Figure 26 for the application circuit diagram.
9 CP5 High Voltage Supply. See Figure 26 for the application circuit diagram.
10
RSVD
Reserved. This pin must be connected to DVSS.
11 AVSS Analog Ground.
12
RSVD
Reserved. This pin must be connected to DVSS.
13 DVSS Digital Signal Ground.
14 AVDD Analog Regulated Voltage. See Figure 26 for the application circuit diagram.
15
MOSI
Master Out/Slave In.
16
SCLK
SPI Clock.
ADXRS453
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Rev. 0 | Page 5 of 32
5 Page 
NOISE PERFORMANCE
The ADXRS453 noise performance is very consistent from
device to device and varies very predictably with temperature.
Table 6 contains statistical noise data at three temperature
points for a large population of ADXRS453 devices (more than
3000 parts from several manufacturing lots).
Table 6. Statistical Noise Data
Noise (°/sec/√Hz)
Temperature
Mean
Standard Deviation
−40°C
0.0109
0.0012
+25°C
0.0149
0.0015
+105°C
0.0222
0.0019
ADXRS453
Noise increases fairly linearly with temperature, as shown in
Figure 24.
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
–50 0
50 100
TEMPERATURE (°C)
Figure 24. Noise Density vs. Temperature, 16 Devices
150
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