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PDF UBA3077HN Data sheet ( Hoja de datos )
| Número de pieza | UBA3077HN | |
| Descripción | Three-channel switched-mode LED driver | |
| Fabricantes | NXP Semiconductors | |
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UBA3077HN
Three-channel switched-mode LED driver
Rev. 1 — 8 February 2011
Objective data sheet
1. General description
The UBA3077HN is a high efficiency LED driver in an HVQFN40 package for general LED
lighting or backlighting LCD displays.
Operating from a supply of 10 V to 42 V, it can drive up to 3 strings of 20 LEDs each. The
low voltage circuitry is powered by an external 5 V voltage supply.
The chip can operate autonomously or be controlled via a 400 kHz I2C-bus.
The peak current in each string is fixed by an external resistor. Three independent
Pulse-Width Modulated (PWM) signals are available for dimming purposes. These PWM
signals are delivered either directly by the graphic processor (direct control mode) to the
pins PWM1, PWM2 and PWM3, or generated on-board based on data sent via the
I2C-bus interface.
Each LED string is supplied by its own boost converter delivering an output voltage from
VIN up to 75 V. The switching frequency is 500 kHz.
A power saving mode is entered when all PWM signals stay LOW for a period longer than
1 s.
Several protection mechanisms are available: overvoltage, short-circuit and open LED,
overcurrent, UnderVoltage LockOut (UVLO) and overtemperature with an advanced
adaptive protection. An error self-recovery (hiccup) mechanism is available with
programmable delay time via an external capacitor.
2. Features and benefits
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Three-channel LED backlight driver
Up to 150 mA per channel
±2 % absolute LED current accuracy Peak LED current programmable with
and channel-to-channel matching
external resistor
External power supply voltage from 10 V Three boost converters from VIN up to
to 42 V and 5 V for low voltage circuitry 75 V output voltage
Constant 500 kHz frequency peak
High efficiency up to 90 %
current mode control
Low value output capacitor (2 μF)
14-bit PWM dimming (either defined by
system-generated PWMs, or internally
generated) from 2.0 kHz to 24 kHz (duty
cycle from 0.1 % to 100 %)
Accurate internal oscillator
All power FETs integrated
1 page  
NXP Semiconductors
7. Pinning information
7.1 Pinning
UBA3077HN
Three-channel switched-mode LED driver
terminal 1
index area
NC1 1
LX2 2
PGND12 3
VSYNC 4
GND 5
INT 6
FB1 7
NC2 8
LX1 9
NC3 10
UBA3077HN
Transparent top view
Fig 2. Pin configuration (HVQFN40)
30 NC6
29 LX3
28 PGND32
27 FB3
26 SAD1
25 NC5
24 NC4
23 SAD0
22 SCL
21 SDA
001aan132
7.2 Pin description
Table 3. Pin description
Symbol Pin Type
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NC1
LX2
PGND12
VSYNC
GND
INT
FB1
NC2
LX1
NC3
PGND11
VOUT1
VDD(IO)
PWM1
1-
2 power
3 supply
4 input
5 input
6 output
7 power
8-
9 power
10 -
11 supply
12 power
13 supply
14 input
Reset Description
state
- not connected (leave unconnected)
- channel 2 boost converter switch output
- channel 1 LED current source ground
- PWM duty cycle value update signal in I2C-bus mode
- connect to the global ground
H interrupt signal to the host (open-drain)
- channel 1 LED current source output
- not connected (leave unconnected)
- channel 1 boost converter switch output
- not connected (leave unconnected)
- channel 1 boost converter switch ground
- channel 1 boost converter output voltage
- reference and supply voltage for the host interface
signals (from 1.8 V to 5 V)
- channel 1 PWM input signal
UBA3077HN
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 February 2011
© NXP B.V. 2011. All rights reserved.
5 of 25
5 Page 
NXP Semiconductors
UBA3077HN
Three-channel switched-mode LED driver
Table 5. Register descriptions
Address Register
Bit Symbol
06h
Clock division 7
VSYNCPOL
6 PWMSEL
5 VSYNC_EN
4 RESERVED
3 to 0 PLLMSB[3:0]
Access Value at
reset
R/W 0
R/W 0
R/W 0
--
R/W 0010
Description
0: VSYNC signal active HIGH
1: VSYNC signal active LOW
0: external PWM selected (direct control
mode)
1: I2C-bus PWM selected
0: immediate PWM duty cycle value change
1: PWM duty cycle value change on VSYNC
signal state as defined by VSYNCPOL
-
PWM PLL MSB division code
8.3 State diagram
The UBA3077HN has the following modes:
• Reset
• Sleep
• Active
• Adaptive thermal
• Hiccup
8.4 Reset mode
The chip enters the reset state at power start-up phase or as soon as VDD falls below the
VDD POR threshold voltage (VPOR). All registers are cleared to their default value.
If VDD is below the rising edge threshold voltage, the UBA3077HN remains in Reset
mode.
8.5 Sleep mode
If all PWM input signals or internally generated PWM signals based on register settings
stay LOW for more than 1 s, the circuit enters Sleep mode. In this mode, the boost
converters are off and the chip activity is reduced to decrease the current consumption to
less than 2.8 mA.
When one of the PWM signals re-activates, the UBA3077HN enters Active mode provided
that a protection has not been triggered.
8.6 Active mode
www.DataSheet4U.com
This is the normal operating mode where all supply conditions are correct and no
abnormal event detected.
In Active mode, the I2C-bus interface and all registers are fully accessible. DC-to-DC
boost converter and LED current sources are operational and react to PWM signals as
requested.
UBA3077HN
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 February 2011
© NXP B.V. 2011. All rights reserved.
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