PDF ADuC7121 Data sheet ( Hoja de datos )

Número de pieza	ADuC7121
Descripción	Precision Analog Microcontroller 12-Bit Analog I/O ARM7TDMI MCU
Fabricantes	Analog Devices
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Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU ADuC7121 FEATURES Software-triggered in-circuit reprogrammability Analog input/output 9-channel, 12-bit, 1 MSPS ADC 2 differential pairs with input PGA 7 general-purpose inputs (differential or single-ended) Fully differential and single-ended modes 0 V to VREF analog input range 5 low noise current digital-to-analog converters (IDACs) 250 mA, 200 mA, 80 mA, 45 mA, 20 mA 4 × 12-bit voltage output DACs On-chip voltage reference On-chip temperature sensor Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 41.78 MHz On-chip peripherals UART, 2 × I2C and SPI serial I/O 32-pin GPIO port 4× general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs Power Specified for 3 V operation Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz Packages and temperature range 7 mm × 7 mm 108-ball CSP_BGA Fully specified for –10°C to +95°C operation Tools Low cost QuickStart development system Full third party support 41.78 MHz PLL with programmable divider Memory 126 kB flash/EE memory, 8 kB SRAM APPLICATIONS Optical modules—tunable laser In-circuit download, JTAG-based debug FUNCTIONAL BLOCK DIAGRAM AVDD 3.3V AGND DAC0 DAC1 DAC2 DAC3 IDAC0 IDAC1 IDAC2 IDAC3 IDAC4 PADC0N PADC0P PADC1N PADC1P ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10/AINCM PGA PGA TEMPERATURE SENSOR ADuC7121 1MSPS 12-BIT SAR ADC OSC WAKE-UP TIMER WD TIMER VIC PLA PLL POR PWM 3× GP TIMERS 126kB FLASH (63k × 16-BIT) 8kB SRAM (2k × 32-BIT) LDO ARM7 TDMI UART JTAG GPIO CONTROL SPI I2C × 2 www.DataSheet4U.com INTERNAL REFERENCE BUF VREF_1.2 VREF_2.5 P0.0 TO P0.7 P1.0 TO P1.7 Figure 1. P2.0 TO P2.7 P3.0 TO P3.7 IOVDD IOGND XTALI XTALO RST TDO TDI TCK TMS TRST Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. 1 page ADuC7121 SPECIFICATIONS AVDD = IOVDD = 3.0 V to 3.6 V, PVDD = 2.0 V ± 5%, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −10°C to +95°C, unless otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy1, 2 Resolution Integral Nonlinearity Min Typ 5 12 ±0.6 Max ±2 Unit μs Test Conditions/Comments Eight acquisition clocks and fADC/2 Bits LSB 2.5 V internal reference, not production tested for PADC0 and PADC1 channels Differential Nonlinearity3, 4 ±0.5 +1.4/−0.99 LSB 2.5 V internal reference, guaranteed monotonic DC Code Distribution ENDPOINT ERRORS5 Offset Error All Channels Except IDACx Channels IDACx Channels Only 1 ±2 1 Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE ±1 ±2 ±1 Signal-to-Noise Ratio (SNR) 69 Total Harmonic Distortion (THD) −78 Peak Harmonic or Spurious Noise −75 Channel-to-Channel Crosstalk −80 ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode 0.15 Leakage Current ±0.2 Input Capacitance 20 20 PADC0x INPUT Full-Scale Input Range Input Leakage at PADC0x4 Resolution 20 0.15 11 www.DaGtaaSinheEerrto4rU4 .com Gain Drift4 Offset4 Offset Drift4 PADC0x Compliant Range 3 30 0.1 LSB ADC input is a dc voltage Internally unbuffered channels ±5 LSB % of full scale LSB ±5 LSB LSB fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS, internally unbuffered channels dB Includes distortion and noise components dB dB dB Measured on adjacent channels VCM6 ± VREF/2 0 to VREF AVDD − 1.5 ±1 1000 2 1 50 6 60 AVDD − 1.2 V V V μA pF pF μA nA Bits % ppm/°C nA pA/°C V See Table 38 Buffer bypassed Buffer enabled During ADC acquisition buffer bypassed During ADC acquisition buffer enabled 28.3 kΩ resistor, PGA gain = 3, acquisition time = 3.2 μs, pseudo differential mode 0.1% accuracy, 5 ppm external resistor for current to voltage PGA offset not included Rev. 0 \| Page 5 of 96 5 Page Table 4 SPI Master Mode Timing (Phase Mode = 1) Parameter Description tSL SPICLK low pulse width tSH SPICLK high pulse width tDAV Data output valid after SPICLK edge tDSU Data input setup time before SPICLK edge1 tDHD Data input hold time after SPICLK edge tDF Data output fall time tDR Data output rise time tSR SPICLK rise time tSF SPICLK fall time Min 1 × tUCLK 2 × tUCLK 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK 5 5 5 5 ADuC7121 Max Unit ns ns 25 ns ns ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns SPICLK (POLARITY = 0) SPICLK (POLARITY = 1) MOSI MISO tSH tSL tDAV tDF MSB tSR tDR BIT 6 TO BIT 1 MSB IN BIT 6 TO BIT 1 tDSU tDHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) tSF LSB LSB IN www.DataSheet4U.com Rev. 0 \| Page 11 of 96 11 Page

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