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PDF HY5S5B6ELF-HE Data sheet ( Hoja de datos )

Número de pieza HY5S5B6ELF-HE
Descripción 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
Fabricantes Hynix Semiconductor 
Logotipo Hynix Semiconductor Logotipo



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No Preview Available ! HY5S5B6ELF-HE Hoja de datos, Descripción, Manual

256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O
Document Title
4Bank x 4M x 16bits Synchronous DRAM
Revision History
Revision No.
History
0.1 Initial Draft
0.2 Modification of IDD Current
0.3
Modification of IDD3P & IDD3PS
IDD3P / IDD3PS : 3mA / 2mA --> 5mA / 5mA
1.0 Final revision
Draft Date
Aug. 2004
Oct. 2004
Jan. 2005
Jul. 2005
Remark
Preliminary
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Jul. 2005
1

1 page




HY5S5B6ELF-HE pdf
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 16 I/O Mobile Synchronous DRAM
PASR
Extended
Mode
Register
Self refresh
logic & timer
Internal Row
Counter
CLK 4Mx16 Bank 3
CKE
Row Active
Row
Pre
4Mx16 Bank 2
4Mx16 Bank 1
CS
Decoder
4Mx16 Bank 0
RAS
CAS
WE
U/LDQM
Refresh
Column Active
Column
Pre
Decoder
Memory
Cell
Array
Column decoders
DQ0
DQ15
Bank Select
Column Add
Counter
A0 Address
A1
Register
Burst
Counter
A12
BA1
Mode Register
CAS Latency
Data Out Control
BA0
Rev 1.0 / Jul. 2005
5

5 Page





HY5S5B6ELF-HE arduino
1
256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6ELF(P)-xE Series
COMMAND TRUTH TABLE
Function
Mode Register Set
Extended Mode Register Set
No Operation
Device Deselect
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst stop
Data Write/Output Enable
Data Mask/Output Disable
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Precharge Power Down Entry
Precharge Power Down Exit
Clock Suspend Entry
Clock Suspend Exit
Deep Power Down Entry
Deep Power Down Exit
CKEn-1 CKEn
HX
HX
HX
HX
HX
HX
HX
HX
HX
HX
HX
HX
HX
HX
HH
HL
LH
HL
LH
HL
LH
HL
LH
CS
RAS
CAS
WE
DQM
ADDR
A10
/AP
BA Note
LL LL X
Op Code
2
LL LL X
Op Code
2
LH HH X
X
HX
XX
X
X
LL
HH
X Row Address V
LH LH
Column L
V
L H L H X Column H V
L H L L X Column L V
L H L L X Column H V
LL HL X
X HX
LL HL X
X LV
LH
HL
X
X
X XX
X VX
LL
LH X
X
LL
LH X
X
HX
XX
X X1
LH HH
HX
LH
XX
HH
X
X
HX
LH
XX
HH
X
X
HX
LV
XX
VV
X
X
X XX
LH
HL
X
X
X XX
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Rev 1.0 / Jul. 2005
11

11 Page







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