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PDF HY5S5B2CLFP-HE Data sheet ( Hoja de datos )
| Número de pieza | HY5S5B2CLFP-HE | |
| Descripción | 256M (8Mx32bit) Mobile SDRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O
Specification of
256M (8Mx32bit) Mobile SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x32
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.5 / Aug. 2008
1
1 page  
11
256Mbit (8Mx32bit) Mobile SDR Memory
HY5S5B2CLF(P) Series
FEATURES
● Standard SDRAM Protocol
● Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
● MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write
for that bank is performed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V
● LVCMOS compatible I/O Interface
● Low Voltage interface to reduce I/O power
● Programmable burst length: 1, 2, 4, 8 or full page
● Programmable Burst Type: sequential or interleaved
● Programmable CAS latency of 3 or 2
● Programmable Drive Strength
● Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
● -25oC ~ 85oC Operation Temperature
- Extended Temp.: -25oC ~ 85oC
● Package Type: 90ball, 0.8mm pitch FBGA (Lead Free, Lead)
HY5S5B2CLFP: Lead Free
Rev 1.5 / Aug. 2008
5
5 Page 
11
256Mbit (8Mx32bit) Mobile SDR Memory
HY5S5B2CLF(P) Series
DC CHARACTERISTICS II (TA= -25 to 85oC)
Parameter
Symbol
Test Condition
Speed
Unit Note
166MHz 133MHz 133MHz
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
60
50
50 mA 1
Precharge Standby Cur- IDD2P CKE ≤ VIL(max), tCK = min
rent
in Power Down Mode IDD2PS CKE ≤ VIL(max), tCK = ∞
0.3 mA
0.3 mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= min
Precharge Standby Cur- IDD2N
rent
in Non Power Down
Input signals are changed one time
during
2clks.
10
mA
Mode
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
1
Active Standby Current IDD3P CKE ≤ VIL(max), tCK = min
in Power Down Mode IDD3PS CKE ≤ VIL(max), tCK = ∞
3
mA
3
CKE ≥ VIH(min), CS ≥ VIH(min), tCK
= min
Active Standby Current
IDD3N
Input signals are changed one time
during
15
in Non Power Down
2clks.
mA
Mode
All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
10
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
65 60 60 mA 1
Auto Refresh Current IDD5 tRFC ≥ tRFC(min),
110 mA
Self Refresh Current
IDD6 CKE ≤ 0.2V
See Next Page
mA 2
Standby Current in
Deep Power Down Mode
IDD7
See p.49~50
10 uA
Note:
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. See the tables of next page for more specific IDD6 current values.
Rev 1.5 / Aug. 2008
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HY5S5B2CLFP-HE.PDF ] | |
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