PDF HY5S2B6DLFP-BE Data sheet ( Hoja de datos )

Número de pieza	HY5S2B6DLFP-BE
Descripción	4Banks x 2M x 16bits Synchronous DRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History 0.1 Initial Draft 0.2 Deleted Preliminary 0.3 Changed Operation Voltage : 1.65(min) -> 1.70(min) Draft Date Dec. 2003 May. 2004 Feb. 2005 Remark Preliminary This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Feb. 2005 1 1 page 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Low Power Synchronous DRAM PASR Extended Mode Register Self refresh logic & timer Internal Row Counter CLK 2Mx16 BANK 3 CKE Row Active Row Pre 2Mx16 BANK 2 2Mx16 BANK 1 CS Decoder 2Mx16 BANK 0 RAS CAS WE U/LDQM Refresh Column Active Column Pre Decoder Memory Cell Array Column decoders DQ0 DQ15 Bank Select Column Add Counter A0 Address A1 Register Burst Counter A11 BA1 Mode Register CAS Latency Data Out Control BA0 Rev. 0.3 / Feb. 2005 5 5 Page 1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Current State CS RAS CAS WE Command BA0/ BA1 A11-A0 LL L L OP CODE LL LH X X L L H L BA X L L H H BA Row Add. idle L H L L BA LH L H LHHH BA X Col Add. A10 Col Add. A10 X HX X X X X LL L L LL LH LLHL L L HH Row Active L H L L LH L H LHHH HX X X LL L L LL LH OP CODE XX BA X BA Row Add. BA Col Add. A10 BA Col Add. A10 XX XX OP CODE XX L L H L BA X Read L L HH LH L L BA BA LH L H LHHH BA X Row Add. Col Add. A10 Col Add. A10 X Description Action Notes Mode Register Set Auto or Self Refresh Precharge Bank Activate Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row 14 5 Write/WriteAP ILLEGAL 4 Read/ReadAP ILLEGAL 4 No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write : optional AP(A10=H) Start Read : optional AP(A10=H) No Operation No Operation ILLEGAL ILLEGAL Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst 3 3 13,14 13 7 4 6 6 13,14 13 4 8,9 8 Rev. 0.3 / Feb. 2005 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HY5S2B6DLFP-BE	4Banks x 2M x 16bits Synchronous DRAM	Hynix Semiconductor

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