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PDF HYMD1166458-H Data sheet ( Hoja de datos )
| Número de pieza | HYMD1166458-H | |
| Descripción | 16Mx64 Unbuffered DDR Sdram Dimm | |
| Fabricantes | Hynix Semiconductor | |
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HYMD1166458-H/L
16Mx64 Unbuffered DDR SDRAM DIMM
DESCRIPTION
PRELIMINARY
Hynix HYMD1166458-H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Mod-
ules (DIMMs) which are organized as 16Mx64 high-speed memory arrays. Hynix HYMD1166458-H/L series consists of
eight 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD1166458-H/L
series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for
easy interchange and addition.
Hynix HYMD1166458-H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations
referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD1166458-H/L series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM
type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 128MB (16M x 64) Unbuffered DDR DIMM based on
16Mx8 DDR SDRAM
• JEDEC Standard 184-pin dual in-line memory module
(DIMM)
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
• Data inputs on DQS centers when write (centered
DQ)
• Data strobes synchronized with output data for read
and input data for write
• Programmable CAS Latency 2 / 2.5 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• 4096 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD1166458-H
HYMD1166458-L
Power Suppy
VDD=2.5V
VDDQ=2.5V
Clock Frequency
133MHz (*DDR266B)
100MHz (*DDR200)
Interface
SSTL_2
Form Factor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
www.DataSheet4U.com
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.1.3/Apr.01
1 page  
HYMD1166458-H/L
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS=0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (RT)
Series Resistor (RS)
Output Load Capacitance for Access Time Measurement (CL)
Value
VDDQ x 0.5
VDDQ x 0.5
VREF + 0.31
VREF - 0.31
VREF
VTT
1.5
1
50
25
30
Unit
V
V
V
V
V
V
V
V/ns
Ω
Ω
pF
www.DataSheet4U.com
Rev.1.3/Apr.01
5
5 Page 
HYMD1166458-H/L
.11 This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps ps
0.5 0 0
0.4 +75 +75
0.3
+150
+150
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF
+/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV ps ps
+280
+50 +50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS
slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate1=0.5V/ns
and Slew Rate2=0.4V/n then the Delta Inverse Slew Rate=-0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps ps
0 00
+/-0.25
+50 +50
+/- 0.5
+100
+100
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
15. tDAL=(tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK
is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK=7.5 ns,
tDAL=(15 ns / 7.5 ns) + (20 ns / 7.5 ns)=(2.00) + (2.67)
Round up each non-integer to the next highest integer:=(2) + (3), tDAL=5 clocks
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS -
BL/2 x tCK.
www.DataSheet4U.com
Rev.1.3/Apr.01
11
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