HYMD116645DL8J Datasheet PDF - Hynix Semiconductor
| Part Number | HYMD116645DL8J | |
| Description | Unbuffered DDR SDRAM DIMM | |
| Manufacturers | Hynix Semiconductor | |
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DESCRIPTION
16Mx64 bits
Unbuffered DDR SDRAM DIMM
HYMD116645D(L)8J
Hynix HYMD116645D(L)8J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory
Modules(DIMMs) which are organized as 16Mx64 high-speed memory arrays. Hynix HYMD116645D(L)8J series con-
sists of eight 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.Hynix
HYMD116645D(L)8J series provide a high performance 8-byte interface in 5.25" width form factor of industry standard.
It is suitable for easy interchange and addition.
Hynix HYMD116645D(L)8J series is designed for high speed of up to 200MHz and offers fully synchronous operations
referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD116645D(L)8J series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 128MB (16M x 64) Unbuffered DDR DIMM based on • Data(DQ), Data strobes and Write masks latched on
16Mx8 DDR SDRAM
both rising and falling edges of the clock
• JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
• Data inputs on DQS centers when write (centered
DQ)
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• 2.6V +/- 0.1V VDD and VDDQ Power supply for
DDR400
• Data strobes synchronized with output data for read
and input data for write
• Programmable CAS Latency 3/ 2 / 2.5 supported
• All inputs and outputs are compatible with SSTL_2
interface
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Fully differential clock operations (CK & /CK) with
125MHz/133MHz/166MHz/200MHz
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• tRAS Lock-out function supported
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• 4096 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
Power Supply
Clock Frequency Interface
Form Factor
HYMD116645D(L)8J-D43
HYMD116645D(L)8J-D4
HYMD116645D(L)8J-J
www.DataSheet4U.com
VDD=VDDQ=2.6V
VDD=VDDQ=2.6V
VDD=VDDQ=2.5V
200MHz (DDR400)
200MHz (DDR400)
166MHz (DDR333)
SSTL_2
SSTL_2
SSTL_2
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.0 / Apr. 2003
1
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HYMD116645D(L)8J
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
0.7
0.5*VDDQ-0.2
VREF - 0.31
VDDQ + 0.6
0.5*VDDQ+0.2
V
V
V
V
1
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (RT)
Series Resistor (RS)
Output Load Capacitance for Access Time Measurement (CL)
Value
VDDQ x 0.5
VDDQ x 0.5
VREF + 0.31
VREF - 0.31
VREF
VTT
1.5
1
50
25
30
Unit
V
V
V
V
V
V
V
V/ns
Ω
Ω
pF
www.DataSheet4U.com
Rev. 0.0 / Apr. 2003
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for HYMD116645DL8J electronic component. |
| Information | Total 18 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ HYMD116645DL8J.PDF Datasheet ] | |
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