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PDF HYMD116645B8J-J Data sheet ( Hoja de datos )
| Número de pieza | HYMD116645B8J-J | |
| Descripción | Unbuffered DDR SDRAM DIMM | |
| Fabricantes | Hynix Semiconductor | |
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DESCRIPTION
16Mx64 bits
Unbuffered DDR SDRAM DIMM
HYMD116645B(L)8J-J
Hynix HYMD116645B(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory
Modules(DIMMs) which are organized as 16Mx64 high-speed memory arrays. Hynix HYMD116645B(L)8J-J series
consists of eight 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix
HYMD116645B(L)8J-J series provide a high performance 8-byte interface in 5.25" width form factor of industry stan-
dard. It is suitable for easy interchange and addition.
Hynix HYMD116645B(L)8J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera-
tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD116645B(L)8J-J series incorporates SPD(serial presence detect). Serial presence detect function is
implement-ed via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden-
tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 128MB (16M x 64) Unbuffered DDR DIMM based on • Data inputs on DQS centers when write (centered
16Mx8 DDR SDRAM
DQ)
• JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
• Data strobes synchronized with output data for read
and input data for write
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• Programmable CAS Latency 2 / 2.5 supported
• All inputs and outputs are compatible with SSTL_2
interface
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Fully differential clock operations (CK & /CK) with
• tRAS Lock-out function supported
100MHz/125MHz/133/166MHz
• Internal four bank operations with single pulsed RAS
•
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
•
Auto refresh and self refresh supported
of the clock
• 4096 refresh cycles / 64ms
• Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
ORDERING INFORMATION
Part No.
HYMD116645B(L)8J-J
Power Supply
VDD=2.5V
VDDQ=2.5V
Clock Frequency
166MHz (*DDR333)
Interface
SSTL_2
Form Factor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
* JEDEC Defined Specifications compliant
www.DataSheet4U.com
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3/Jun. 02
1
1 page  
HYMD116645B(L)8J-J
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS=0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (RT)
Series Resistor (RS)
Output Load Capacitance for Access Time Measurement (CL)
Value
VDDQ x 0.5
VDDQ x 0.5
VREF + 0.31
VREF - 0.31
VREF
VTT
1.5
1
50
25
30
Unit
V
V
V
V
V
V
V
V/ns
W
W
pF
www.DataSheet4U.com
Rev. 0.3/Jun. 02
5
5 Page 
HYMD116645B(L)8J-J
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.
11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps ps
0.5 0 0
0.4 +75 +75
0.3
+150
+150
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF
+/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV ps ps
+280
+50 +50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS
slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns
and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps ps
0 00
+/-0.25
+50 +50
+/- 0.5
+100
+100
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
15. tDAL = (tWR / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK
is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK
17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
www.DataSheet4U.com
Rev. 0.3/Jun. 02
11
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