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PDF XMEGAD Data sheet ( Hoja de datos )
| Número de pieza | XMEGAD | |
| Descripción | Interrupts and Programmable Multi-level Interrupt Controller | |
| Fabricantes | ATMEL Corporation | |
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This document contains complete and detailed description of all modules included in
the AVR® XMEGATM D Microcontroller family. The XMEGA D is a family of low power,
high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the
AVR enhanced RISC architecture. The available XMEGA D modules described in this
manual are:
• AVR CPU
• Memories
• Event System
• System Clock and Clock options
• Power Management and Sleep Modes
• System Control and Reset
• WDT - Watchdog Timer
• Interrupts and Programmable Multi-level Interrupt Controller
• PORT - I/O Ports
• TC - 16-bit Timer/Counter
• AWeX - Advanced Waveform Extension
• Hi-Res - High Resolution Extension
• RTC - Real Time Counter
• TWI - Two Wire Serial Interface
• SPI - Serial Peripheral Interface
• USART - Universal Synchronous and Asynchronous Serial Receiver and Transmitter
• IRCOM - IR Communication Module
• ADC - Analog to Digital Converter
• AC - Analog Comparator
• PDI - Program and Debug Interface
• Memory Programming
• Peripheral Address Map Register Summary
• Interrupt Vector Summary
• Instruction Set Summary
8-bit
XMEGA D
Microcontroller
XMEGA D
MANUAL
Preliminary
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8210B- AVR-04/10
1 page  
XMEGA D
3. AVR CPU
3.1 Features
• 8/16-bit high performance AVR RISC CPU
– 138 instructions
– Hardware multiplier
• 32x8-bit registers directly connected to the ALU
• Stack in RAM
• Stack Pointer accessible in I/O memory space
• Direct addressing of up to 16M bytes of program memory and 16M bytes of data memory
• True 16/24-bit access to 16/24-bit I/O registers
• Efficient support for both 8-, 16- and 32-bit Arithmetic
• Configuration Change Protection of system critical features
3.2 Overview
XMEGA uses the 8/16-bit AVR CPU. The main function of the CPU is to ensure correct program
execution. The CPU is able to access memories, perform calculations and control peripherals.
Interrupt handling is described in a separate section, refer to ”Interrupts and Programmable
Multi-level Interrupt Controller” on page 95 for more details on this.
3.3 Architectural Overview
In order to maximize performance and parallelism, the AVR uses a Harvard architecture with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the Program Memory. This concept enables instructions to be executed
in every clock cycle. For the summary of all AVR instructions refer to ”Instruction Set Summary”
on page 296. For details of all AVR instructions refer to http://www.atmel.com/avr.
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8210B–AVR–04/10
5
5 Page 
XMEGA D
3.10
RAMP and Extended Indirect Registers
In order to access program memory or data memory above 64K bytes, the address or address
pointer must be more than 16-bits. This is done by concatenating one register to one of the X-,
Y- or Z-registers, and this register then holds the most significant byte (MSB) in a 24-bit address
or address pointer.
These registers are only available on devices with external bus interface and/or more than 64K
bytes of program or data memory space. For these devices, only the number of bits required to
address the whole program and data memory space in the device is implemented in the
registers.
3.10.1
RAMPX, RAMPY and RAMPZ Registers
The RAMPX, RAMPY and RAMPZ registers are concatenated with the X-, Y-, and Z-registers
respectively to enable indirect addressing of the whole data memory space above 64K bytes
and up to 16M bytes.
Figure 3-6. The combined RAMPX + X, RAMPY + Y and RAMPZ + Z registers
Bit (Individually)
7
0
RAMPX
Bit (X-pointer)
23
16
Bit (Individually)
7
0
RAMPY
Bit (Y-pointer)
23
16
Bit (Individually)
7
0
RAMPZ
Bit (Z-pointer)
23
16
7
XH
15
7
YH
15
7
ZH
15
07
0
XL
87
0
07
0
YL
87
0
07
0
ZL
87
0
When reading (ELPM) and writing (SPM) program memory locations above the first 128K bytes
of the program memory, RAMPZ is concatenated with the Z-register to form the 24-bit address.
LPM is not affected by the RAMPZ setting.
3.10.2
RAMPD Register
This register is concatenated with the operand to enable direct addressing of the whole data
memory space above 64K bytes. Together RAMPD and the operand will form a 24-bit address.
Figure 3-7. The combined RAMPD + K register
Bit (Individually)
Bit (D-pointer)
70
RAMPD
23 16
15
15
K
0
0
3.10.3 EIND - Extended Indirect Register
EIND is concatenated with the Z-register to enable indirect jump and call to locations above the
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first 128K bytes (64K words) of the program memory.
Figure 3-8. The combined EIND + Z register
Bit (Individually)
7
07
EIND
ZH
Bit (D-pointer)
23
16 15
0
8
70
ZL
70
8210B–AVR–04/10
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XMEGAD.PDF ] | |
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