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PDF FAN6755 Data sheet ( Hoja de datos )

Número de pieza FAN6755
Descripción Highly Integrated Green-Mode PWM Controller
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FAN6755 Hoja de datos, Descripción, Manual

February 2010
FAN6755
Highly Integrated Green-Mode PWM Controller
Features
ƒ Internal High-Voltage Startup
ƒ Low Operating Current (Maximum: 2mA)
ƒ Adaptive Decreasing of PWM Frequency to 23KHz
at Light-Load condition to Improve Light-Load
Efficiency
ƒ Frequency Hopping to Reduce EMI Emission
ƒ Fixed PWM Frequency: 65KHz
ƒ Internal Leading-Edge Blanking
ƒ Built-in Synchronized Slope Compensation
ƒ Auto-Restart Protection : Feedback Open-Loop
Protection (OLP), VDD Over-Voltage Protection
(OVP), Over-Temperature Protection (OTP), and
Line Over-Voltage Protection
ƒ Soft Gate Drive with Clamped Output Voltage: 18V
ƒ VDD Under-Voltage Lockout (UVLO)
ƒ Programmable Constant Power Limit (Full AC
Input Range)
ƒ Internal OTP Sensor with Hysteresis
ƒ Build-in 5ms Soft-Start Function
ƒ Input Voltage Sensing (VIN Pin) for Brown-in/out
Protection with Hysteresis and Line Over-Voltage
Protection
Applications
General-purpose switched-mode power supplies and
flyback power converters, including:
ƒ LCD Monitor Power Supply
ƒ Open-Frame SMPS
Description
This highly integrated PWM controller provides several
features to enhance the performance of flyback
converters.
To minimize standby power consumption, a proprietary
adaptive green-mode function reduces switching
frequency at light-load condition. To avoid acoustic-
noise problems, the minimum PWM frequency is set
above 23kHz. This green-mode function enables the
power supply to meet international power conservation
requirements, such as Energy Star®. With the internal
high-voltage startup circuitry, the power loss caused by
bleeding resistors is also eliminated. To further reduce
power consumption, FAN6755 uses the BiCMOS
process, which allows an operating current of only 2mA.
The standby power consumption can be under 100mW
for most of LCD monitor power supply designs.
FAN6755 integrates a frequency-hopping function that
reduces EMI emission of a power supply with minimum
line filters. Its built-in synchronized slope compensation
achieves a stable peak-current-mode control and
improves noise immunity. The proprietary, external line
compensation ensures constant output power limit over
a wide AC input voltage range from 90VAC to 264VAC.
FAN6755 provides many protection functions. The
internal feedback open-loop protection circuit protects
the power supply from open feedback loop condition or
output short condition. It also has line under-voltage
protection (brownout protection) and over-voltage
protection using an input voltage sensing pin (VIN).
FAN6755 is available in a 7-pin SOP package.
Ordering Information
Part Number
Operating
Temperature Range
www.DataSheet4U.com
FAN6755MY
-40 to +105°C
Eco
Status
Green
Package
7-Lead, Small Outline Integrated
Circuit (SOIC), Depopulated
JEDEC MS-112, .150 Inch Body
Packing Method
Reel & Tape
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
ENERGY STAR® is a registered trademark of the U.S. Department of Energy and the U.S. Environmental Protection Agency.
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
1
www.fairchildsemi.com

1 page




FAN6755 pdf
Electrical Characteristics
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
VDD Section
VOP
VDD-ON
VDD-OFF
UVLO
Continuously Operating Voltage
Start Threshold Voltage
Protection Mode
Normal Mode
IDD-ST
IDD-OP
IDD-OLP
VDD-OLP
Startup Current
Operating Supply Current
Internal Sink Current
Threshold Voltage on VDD for HV
JFET Turn-On
VDD-OVP
tD-VDDOVP
VDD Over-Voltage Protection
VDD Over-Voltage Protection
Debounce Time
VDD-ON – 0.16V
VDD=15V, GATE Open
VTH-OLP+0.1V
Min. Typ. Max. Units
22 V
15 16 17
V
9 10 11 V
6.8 7.8
8.8
V
30 µA
2 mA
30 60 90 µA
6.5 7.5 8.0
V
25 26 27
V
75 125 200
µs
Figure 5. VDD Behavior
Continued on the following page…
www.DataSheet4U.com
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
5
www.fairchildsemi.com

5 Page





FAN6755 arduino
Functional Description
Startup Current
For startup, the HV pin is connected to the line input
(1N4007 / 100Krecommended) or bulk capacitor
through a resistor, RHV. Startup current drawn from pin
HV (typically 3.5mA) charges the hold-up capacitor
through the diode and resistor. When the VDD capacitor
level reaches VDD-ON, the startup current switches off. At
this moment, the VDD capacitor only supplies the
FAN6755 to maintain VDD before the auxiliary winding of
the main transformer to provide the operating current.
Operating Current
Operating current is around 2mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Green-Mode Operation
The proprietary green-mode function provides an off-
time modulation to reduce the switching frequency in
light-load and no-load conditions. The on time is limited
for better abnormal or brownout protection. VFB, which is
derived from the voltage feedback loop, is taken as the
reference. Once VFB is lower than the threshold voltage,
switching frequency is continuously decreased to the
minimum green-mode frequency of around 23KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current sense signal and VFB, the feedback voltage.
When the voltage on the SENSE pin reaches around
VCOMP=(VFB–0.6)/4, a switch cycle is terminated
immediately. VCOMP is internally clamped to a variable
voltage around 0.83V for output power limit.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 5.5ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6755 inserts a synchronized positive-going ramp at
every switching cycle.
Constant Output Power Limit
For constant output power limit over universal input-
voltage range, the peak-current threshold is adjusted by
the voltage of the VIN pin. Since the VIN pin is
connected to the rectified AC input line voltage through
the resistive divider, a higher line voltage generates a
higher VIN voltage. The threshold voltage decreases as
VIN increases, making the maximum output power at
high-line input voltage equal to that at low-line input.
The value of R-C network should not be so large that it
affects the power limit (shown in Figure 21). Usually, R
and C should be less than 100Ω and 470pF,
respectively.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16V and 7.8V in normal mode. During startup, the
hold-up capacitor must be charged to 16V through the
www.DatasSthaeretut4pUr.ecsoimstor to enable the IC. The hold-up capacitor
continues to supply VDD before the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 7.8V during startup. This
UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during startup.
Figure 21. Current-Sense R-C Filter
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
11
www.fairchildsemi.com

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