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Número de pieza | NTP13N10 | |
Descripción | Power MOSFET ( Transistor ) | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! NTP13N10
Preferred Device
Power MOSFET
13 A, 100 V, N−Channel
Enhancement−Mode TO−220
Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
• IDSS and RDS(on) Specified at Elevated Temperature
• Pb−Free Package is Available
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Drain−to−Source Voltage (RGS = 1.0 MΩ)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous @ TA 25°C
− Continuous @ TA 100°C
− Pulsed (Note 1)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
100
100
"20
"30
13
8.0
39
64.7
0.43
Vdc
Vdc
Vdc
Adc
W
W/°C
Operating and Storage Temperature Range
TJ, Tstg
−55 to
+175
°C
Single Drain−to−Source Avalanche Energy −
Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
IL(pk) = 13 A, L = 1.0 mH, RG = 25 Ω)
EAS
mJ
85
Thermal Resistance
− Junction−to−Case
RθJC
°C/W
2.32
Maximum Lead Temperature for Soldering
TL 260 °C
Purposes, 1/8″ from case for 10 seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
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*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 6
1
http://onsemi.com
VDSS
100 V
RDS(ON) TYP
165 mΩ @ 10 V
N−Channel
D
ID MAX
13 A
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
4
12
3
TO−220AB
CASE 221A
STYLE 5
13N10
AYWW
1
Gate
3
Source
2
Drain
13N10
A
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NTP13N10
TO−220AB
50 Units/Rail
NTP13N10G
TO−220AB
(Pb−Free)
50 Units/Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
NTP13N10/D
1 page NTP13N10
20
18
16
14 VDS
QT
100
90
80
70
12 60
10
8
6
Q1
VGS
50
Q2 40
30
4 20
2
ID = 13 A
TJ = 25°C
10
00 2 4 6 8 10 12 140
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1000
100
10
VDD = 80 V
ID = 13 A
VGS = 10 V
tr
tf
td(off)
td(on)
1
1 10
RG, GATE RESISTANCE (Ω)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
12
VGS = 0 V
10 TJ = 25°C
100
8
6
4
2
0
0.4 0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
www.DtartaavSehreseet4aUny.colomad line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
5 Page |
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PDF Descargar | [ Datasheet NTP13N10.PDF ] |
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