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PDF SC18IS603 Data sheet ( Hoja de datos )
| Número de pieza | SC18IS603 | |
| Descripción | I2C-bus to SPI bridge | |
| Fabricantes | NXP Semiconductors | |
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SC18IS602/602B/603
I2C-bus to SPI bridge
Rev. 04 — 11 March 2008
Product data sheet
1. General description
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The SC18IS602/602B and SC18IS603 are designed to serve as an interface between a
standard I2C-bus of a microcontroller and an SPI bus. This allows the microcontroller to
communicate directly with SPI devices through its I2C-bus. The SC18IS602/602B/603
operates as an I2C-bus slave-transmitter or slave-receiver and an SPI master. The
SC18IS602/602B/603 controls all the SPI bus-specific sequences, protocol, and timing.
The SC18IS602/602B has its own internal oscillator, while the SC18IS603 requires an
external clock source for operation. SC18IS602 and SC18IS603 do not support SS2
function as SPI slave select signal; this pin can only be used as GPIO2.
2. Features
I I2C-bus slave interface operating up to 400 kHz
I SPI master operating up to 1.8 Mbit/s (SC18IS602/602B) or 4 Mbit/s (SC18IS603)
I 200-byte data buffer
I Up to four slave select outputs
I Up to four programmable I/O pins
I Operating supply voltage: 2.4 V to 3.6 V
I Low power mode
I Internal oscillator option
I Active LOW interrupt output
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 that exceeds 100 mA
I Very small 16-pin TSSOP
3. Applications
I Converting I2C-bus to SPI
I Adding additional SPI bus controllers to an existing system
1 page  
NXP Semiconductors
SC18IS602/602B/603
I2C-bus to SPI bridge
7.1.1 Addressing
slave address
R/W
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Fig 5. Slave address
0 1 0 1 A2 A1 A0 X
fixed
programmable
002aac446
The first seven bits of the first byte sent after a START condition defines the slave address
of the device being accessed on the bus. The eighth bit determines the direction of the
message. A ‘0’ in the least significant position of the first byte means that the master will
write information to a selected slave. A ‘1’ in this position means that the master will read
information from the slave. When an address is sent, each device in a system compares
the first seven bits after the START condition with its address. If they match, the device
considers itself addressed by the master as a slave-receiver or slave-transmitter,
depending on the R/W bit.
A slave address of the SC18IS602/602B/603 is comprised of a fixed and a programmable
part. The programmable part of the slave address enables the maximum possible number
of such devices to be connected to the I2C-bus. Since the SC18IS602/602B/603 have
three programmable address bits (defined by the A2, A1, and A0 pins), it is possible to
have eight of these devices on the same bus.
The state of the A2, A1, and A0 pins are latched at reset. Changes made after reset will
not alter the address.
7.1.2 Write to data buffer
All communications to or from the SC18IS602/602B/603 occur through the data buffer.
The data buffer is 200 bytes deep. A message begins with the SC18IS60x address,
followed by the Function ID. Depending upon the Function ID, zero to 200 data bytes can
follow.
The SC18IS60x will place the data received into a buffer and continue loading the buffer
until a STOP condition is received. After the STOP condition is detected, further
communications will not be acknowledged until the function designated by the Function ID
has been completed.
S SLAVE ADDRESS W A
Fig 6. Write to data buffer
FUNCTION ID
A 0 TO 200 BYTES A P
002aac447
7.1.3 SPI read and write - Function ID 01h to 0Fh
Data in the buffer will be sent to the SPI port if the Function ID is 01h to 0Fh. The Function
ID contains the Slave Select (SS) to be used for the transmission on the SPI port. There
are four Slave Selects that can be used, with each SS being selected by one of the bits in
SC18IS602_602B_603_4
Product data sheet
Rev. 04 — 11 March 2008
© NXP B.V. 2008. All rights reserved.
5 of 25
5 Page 
NXP Semiconductors
SC18IS602/602B/603
I2C-bus to SPI bridge
A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin
contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the
primary source current for a quasi-bidirectional pin that is outputting a 1. wIf wthwis.DpaintaiSsheet4U.com
pulled LOW by an external device, the weak pull-up turns off, and only the very weak
pull-up remains on. In order to pull the pin LOW under these conditions, the external
device has to sink enough current to overpower the weak pull-up and pull the pin below its
input threshold voltage.
The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up
LOW-to-HIGH transitions on a quasi-bidirectional pin when the port latch changes from a
logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks
quickly pulling the pin HIGH.
The quasi-bidirectional pin configuration is shown in Figure 16.
Although the SC18IS602/602B/603 is a 3 V device, most of the pins are 5 V tolerant. If 5 V
is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing
from the pin to VDD causing extra power consumption. Therefore, applying 5 V to pins
configured in quasi-bidirectional mode is discouraged.
A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression
circuit.
2 SYSTEM
CLOCK
CYCLES
VDD
P P very P
strong
weak
weak
pin latch data
VSS
input data
Fig 16. Quasi-bidirectional output configuration
GPIO pin
glitch rejection
002aac548
7.1.11.2 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a
pin configured in this manner must have an external pull-up, typically a resistor tied to
VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.
The open-drain pin configuration is shown in Figure 17.
An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.
SC18IS602_602B_603_4
Product data sheet
Rev. 04 — 11 March 2008
© NXP B.V. 2008. All rights reserved.
11 of 25
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