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Número de pieza | PCS3P73Z01BW | |
Descripción | Wide Frequency range Timing-Safe Peak EMI reduction IC | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PCS3P73Z01BW (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
No Preview Available ! May 2008
rev 0.2
PCS3P73Z01BW
Wide Frequency range Timing-Safe™ Peak EMI reduction IC
General Features
• 1x , LVCMOS Timing-Safe™ Peak EMI Reduction
• Input frequency:
12MHz - 150MHz @ 2.5V
15MHz - 175MHz @ 3.3V
• Output frequency ( Timing-Safe™):
12MHz - 150MHz @ 2.5V
15MHz - 175MHz @ 3.3V
• Analog Spread Selection up to ±1%
• External Input-Output Delay Control option
• Power Down option for Power Save mode
• Supply Voltage: 2.5V±0.2V
3.3V ± 0.3V
• Commercial temperature range
• 8 pin, TSSOP, and TDFN(2X2) COL packages
• The First True Drop-in Solution
delivering a 1x Timing-Safe™ clock. PCS3P73Z01BW has
a Frequency Selection (FS) control that facwiliwtawte.sDsaetaleSchteinegt4U.com
one of the two frequency ranges within the operating
frequency range. Refer to the frequency Selection table for
details. The device has an SSEXTR pin to select different
deviations and associated Input-Output Skew (TSKEW),
depending upon the value of an external resistor connected
between SSEXTR and GND. PCS3P73Z01BW has a
DLY_CTRL for adjusting the Input-Output clock delay,
depending upon the value of capacitor connected at this
pin to GND. PD#/OE provides the Power Down option.
Outputs will be tri-stated when power down is active.
PCS3P73Z01BW operates from a 2.5V/3.3V supply and is
available in an 8 Pin TSSOP, and TDFN (2X2) COL
Packages, over Commercial temperature range.
Functional Description
PCS3P73Z01BW is a 2.5V/3.3V versatile EMI reduction IC
based on PulseCore Semiconductor’s patent pending
Timing-Safe™ technology. PCS3P73Z01BW accepts one
input from an external reference, and locks on to it
Application
PCS3P73Z01BW is targeted for use in Displays, Camera
modules and high speed SDRAM memory interface
systems.
Block Diagram
DLY_CTRL
VDD
SSEXTR
CLKIN
PLL
ModOUT
(Timing-Safe™)
PD#/OE
GND
FS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
1 page May 2008
rev 0.2
Switching Waveforms
Duty Cycle Timing
OUTPUT
VDD/2
t1
t2
VDD/2
All Outputs Rise/Fall Time
OUTPUT
80%
20%
t3
Input - Output Propagation Delay
80%
20%
t4
INPUT
OUTPUT
VDD/2
VDD/2
t6
VDD/2
PCS3P73Z01BW
www.DataSheet4U.com
3.3V
0V
Input-Output Skew
Timing-Safe™
Input
Output
TSKEW -
TSKEW+
One clock cycle
N=1
TSKEW represents input-output skew
when spread spectrum is ON
For example, TSKEW = ± 0.20 for an Input
clock of 12MHz, translates in to
(1/12MHz) * 0.20=16.66nS
Note: Tskew is measured in units of Clock Period
Wide Frequency range Timing-Safe™ Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
5 of 16
5 Page May 2008
rev 0.2
Charts (for VDD=2.5V±0.2V)
I/O Delay Vs Load (DLY_CTRL)
800
2.3V
600
2.5V
2.7V
400 3V
3.3V
200 3.6V
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-200
-400
-600
Capacitance (pF)
Fig23: I/O Delay Vs Load (DLY_CTRL)
(For 12MHz, FS=0)
Charts (for VDD=2.5V±0.2V and 3.3V±0.3V)
I/O Delay Vs Load (DLY_CTRL)
800 2.3V
600 2.5V
2.7V
400 3V
3.3V
200 3.6V
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-200
-400
-600
-800
Capacitance (pF)
Fig25: I/O Delay Vs Load (DLY_CTRL)
(For 33MHz, FS=0)
I/O Delay Vs Load (DLY_CTRL)
800 2.3V
600 2.5V
2.7V
400 3V
3.3V
200 3.6V
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-200
-400
-600
-800
Capacitance (pF)
Fig27: I/O Delay Vs Load (DLY_CTRL)
(For 66MHz, FS=1)
PCS3P73Z01BW
I/O Delay Vs Load (DLY_CTRL)
800 www.D2.3aVtaSheet4U.com
600 2.5V
2.7V
400 3V
3.3V
200 3.6V
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-200
-400
-600
-800
Capacitance (pF)
Fig24: I/O Delay Vs Load (DLY_CTRL)
(For 25MHz, FS=0)
I/O Delay Vs Load (DLY_CTRL)
800 2.3V
600 2.5V
2.7V
400 3V
200 3.3V
3.6V
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-200
-400
-600
-800
-1000
Capacitance (pF)
Fig26: I/O Delay Vs Load (DLY_CTRL)
(For 40MHz, FS=0)
Wide Frequency range Timing-Safe™ Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
11 of 16
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet PCS3P73Z01BW.PDF ] |
Número de pieza | Descripción | Fabricantes |
PCS3P73Z01BW | Wide Frequency range Timing-Safe Peak EMI reduction IC | ON Semiconductor |
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