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PDF NTP60N06L Data sheet ( Hoja de datos )
| Número de pieza | NTP60N06L | |
| Descripción | Power MOSFET 60 Amps / 60 Volts Logic Level | |
| Fabricantes | ON Semiconductor | |
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NTP60N06L, NTB60N06L
Power MOSFET
60 Amps, 60 Volts,
Logic Level
N−Channel TO−220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters, power motor controls and bridge circuits.
Features
• Pb−Free Packages are Available
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
VDSS
VDGR
VGS
VGS
ID
ID
IDM
PD
60
60
"15
"20
Vdc
Vdc
Vdc
60 Adc
42.3
180 Apk
150 W
1.0 W/°C
2.4 W
Operating and Storage Temperature Range
TJ, Tstg −55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 75 Vdc, VGS = 5.0 Vdc,
L = 0.3 mH, IL(pk) = 55 A,VDS = 60 Vdc)
Thermal Resistance,
− Junction−to−Case
− Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS
RqJC
RqJA
TL
454 mJ
°C/W
1.0
62.5
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 3
1
www.DataSheet4U.com
http://onsemi.com
60 AMPERES, 60 VOLTS
RDS(on) = 16 mW
N−Channel
D
G
S
4
4
1
2
3
TO−220AB
CASE 221A
STYLE 5
12
3 D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
NTx60N06LG
AYWW
NTx
60N06LG
AYWW
1
Gate
2
Drain
3
Source
12 3
Gate Drain Source
NTx60N06L
x
A
Y
WW
G
= Device Code
= B or P
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
NTP60N06L/D
1 page  
NTP60N06L, NTB60N06L
6
5
Q1
4
QT
Q2
VGS
1000
tr
tf
3
2
1 ID = 60 A
TJ = 25°C
0
0 10 20 30 40 50
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
100
10
1
td(off)
www.DataSheet4U.com
td(on)
VDS = 30 V
ID = 60 A
VGS = 5 V
10
RG, GATE RESISTANCE (W)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
60
VGS = 0 V
50 TJ = 25°C
40
30
TJ = 150°C
20
TJ = 25°C
10
0
0.3 0.38 0.46 0.54 0.62 0.7 0.78 0.86
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
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| PDF Descargar | [ Datasheet NTP60N06L.PDF ] | |
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