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Número de pieza | NTLJD2104P | |
Descripción | Power MOSFET ( Transistor ) | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! NTLJD2104P
Power MOSFET
−12 V, −4.3 A, mCOOLE Dual P−Channel,
2x2 mm, WDFN package
Features
• WDFN 2x2 mm Package with Exposed Drain Pads for Excellent
Thermal Conduction
• Lowest RDS(on) in 2x2 mm Package
• Footprint Same as SC−88 Package
• Low Profile (<0.8 mm) for Easy Fit in Thin Environments
• Bidirectional Current Flow with Common Source Configuration
• These are Pb−Free Devices
Applications
• Optimized for Battery and Load Management Applications in
Portable Equipment
• Li Ion Battery Charging and Protection Circuits
• Dual High Side Load Switch
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (Note 1)
Steady
State
Power Dissipation
(Note 1)
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
t≤5s
Steady
State
t≤5s
Steady
State
TJ = 25°C
TJ = 85°C
TJ = 25°C
TJ = 25°C
TJ = 25°C
TJ = 85°C
TJ = 25°C
VDSS
VGS
ID
PD
ID
PD
−12
±8.0
−3.5
−2.5
−4.3
1.5
2.3
−2.4
−1.7
0.7
V
V
A
W
A
W
Pulsed Drain Current
tp = 10 ms
IDM
Operating Junction and Storage Temperature TJ, TSTG
−20
−55 to
150
A
°C
Source Current (Body Diode) (Note 2)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
IS −1.5 A
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
of 30 mm2, 2 oz. Cu.
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V(BR)DSS
−12 V
RDS(on) TYP
60 mW @ −4.5 V
85 mW @ −2.5 V
110 mW @ −1.8 V
140 mW @ −1.5 V
190 mW @ −1.3 V
230 mW @ −1.2 V
ID MAX
−3.0 A
−3.0 A
−0.7 A
−0.5 A
−0.2 A
−0.2 A
S1
G1
S2
G2
D1 D2
P−CHANNEL MOSFET P−CHANNEL MOSFET
D2 D1
MARKING
DIAGRAM
Pin 1
WDFN6
CASE 506AN
1
2
JCMG
6
5
3G 4
JC = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
S1 1
D1
6 D1
G1 2
D2 3
D2
5 G2
4 S2
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
October, 2008 − Rev. 2
1
Publication Order Number:
NTLJD2104P/D
1 page NTLJD2104P
TYPICAL CHARACTERISTICS
800
700
Ciss
600
VGS = 0 V
TJ = 25°C
f = 1 MHz
500
400
Coss
300
200
100 Crss
0
0 2 4 6 8 10
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
12
1000
100
VGS = −4.5 V
VDD = −6 V
ID = −3 A
10
td(off)
tf
tr
td(on)
5 QT
8
46
3 −VDS
−VGS
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4
2 QGS
1
QGD
VDS = −6 V
ID = −3 A
TJ = 25°C
2
00
012 345 6
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
100
TJ = 150°C
10
TJ = 25°C
1
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
0.8
0.7 ID = −250 mA
0.6
0.5
0.4
0.3
0.2
−50 −25 0 25 50 75 100 125 150
TJ, TEMPERATURE (°C)
Figure 11. Threshold Voltage
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
30
25 *See Note 2 on Page 1
20
15
10
5
0
0.001 0.01
0.1
1
10 100 1000
SINGLE PULSE TIME (s)
Figure 12. Single Pulse Maximum Power
Dissipation
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NTLJD2104P | Power MOSFET ( Transistor ) | ON Semiconductor |
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