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PDF MAX14886 Data sheet ( Hoja de datos )
| Número de pieza | MAX14886 | |
| Descripción | Dual DisplayPort Graphics Multiplexer | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX14886 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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19-5707; Rev 0; 12/10
EVAALVUAAILTAIOBNLEKIT
Dual DisplayPort Graphics Multiplexerwww.DataSheet4U.com
with HDMI Level Shifter
General Description
The MAX14886 high-speed, low-skew, active redriver
multiplexer is ideal for switching between outputs of
dual-graphics systems and signal conditioning to meet
HDMIK v.1.4 compliance up to 2.25Gbps at an external
HDMI connector. It is used for switching between inte-
grated (e.g., Intel or AMD) and discrete graphics (e.g.,
NVIDIA or ATI GPU). The device is VESA DisplayPortK
Interoperability Guideline v.1.1a-compliant (requires
external DDC logic) and integrates seamlessly with an
external HDMI connector on the motherboard.
The device accommodates differential inputs as low
as 200mV and drives transition minimized differential
signaling (TMDS®) outputs to 1000mV (typ). A precision
resistor on the output level adjust pin (ADJ) allows differ-
entiated output back-termination resistors of 400I (typ)
to better meet HDMI mask jitter compliance, while main-
taining full TMDS swing requirements. The device sup-
ports AC-(DisplayPort) or DC-(HDMI) coupling directly
to the graphics IC and must be DC-coupled to the HDMI
connector. In addition, the device features current back-
flow protection at the HDMI connector and a low-power,
active-high or active-low shutdown mode.
The device operates with a single +3.3V supply, is
specified over the 0NC to +70NC commercial temperature
range, and is available in a 5mm x 5mm, 40-pin TQFN
package.
Applications
Dual Graphics Notebook Computers
Dual Mode DisplayPort to HDMI External
Switches or Adapters
Features
S Single +3.3V Supply
S Meets HDMI v.1.4 Eye Mask Up to 2.25Gbps
S Meets VESA DisplayPort Interoperability Guideline
v.1.1a (Requires External DDC Logic)
S Low-Power Shutdown Mode
Active High or Active Low
S Output Level Adjust (ADJ) for Output Back-
Termination Without Amplitude Loss
S Seamless Integration into Dual-Graphics Systems
with External HDMI Connector
DC-Coupled HDMI Outputs Mate Directly to
HDMI Connector
AC- or DC-Coupled TMDS-Formatted Inputs
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX14886CTL+
0NC to +70NC
40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
3.3V
VAVCC = 3.3V
100nF
VCC
D0AP
D0AN
D0CP
D0CN
50Ω
CKAP
CKAN
CKCP
CKCN
100nF
MAX14886
D0BP
D0BN
CKBP
SEL
EN1
EN2
ADJ
CKBN
GND
3.3kΩ
HDMI is a trademark of HDMI Licensing, LLC.
DisplayPort is a trademark of Video Electronics Standards
Association (VESA).
TMDS is a registered trademark of Silicon Image, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
Dual DisplayPort Graphics Multiplexerwww.DataSheet4U.com
with HDMI Level Shifter
Pin Configuration
TOP VIEW
30 29 28 27 26 25 24 23 22 21
VCC 31
GND 32
20 D2CP
19 D2CN
ADJ 33
18 D1CP
SEL 34
17 D1CN
GND 35
VCC 36
EN2 37
MAX14886
16 VCC
15 D0CP
14 D0CN
EN1 38
GND 39
+
*EP 13 CKCP
12 CKCN
VCC 40
11 GND
1 2 3 4 5 6 7 8 9 10
*CONNECT EP TO GND.
TQFN
(5mm × 5mm × 0.75mm)
PIN
1
2
3
4
5, 10,
11, 21,
26, 32,
35, 39
6
7
8
9
12
13
14
15
16, 31,
36, 40
17
NAME
D0AP
D0AN
D0BP
D0BN
GND
CKAP
CKAN
CKBP
CKBN
CKCN
CKCP
D0CN
D0CP
VCC
D1CN
FUNCTION
Noninverting Input D0 for Channel A
Inverting Input D0 for Channel A
Noninverting Input D0 for Channel B
Inverting Input D0 for Channel B
Ground
Noninverting Input Clock for Channel A
Inverting Input Clock for Channel A
Noninverting Input Clock for Channel B
Inverting Input Clock for Channel B
Inverting Output Clock
Noninverting Output Clock
Inverting Output D0
Noninverting Output D0
Power-Supply Voltage. Bypass VCC
to GND with low-ESR 10nF and
4.7FF ceramic capacitors in parallel
as close as possible to the device.
Recommended on each VCC pin.
Inverting Output D1
Pin Description
PIN NAME
FUNCTION
18 D1CP Noninverting Output D1
19 D2CN Inverting Output D2
20 D2CP Noninverting Output D2
22 D2BP Noninverting Input D2 for Channel B
23 D2BN Inverting Input D2 for Channel B
24 D2AP Noninverting Input D2 for Channel A
25 D2AN Inverting Input D2 for Channel A
27 D1BP Noninverting Input D1 for Channel B
28 D1BN Inverting Input D1 for Channel B
29 D1AP Noninverting Input D1 for Channel A
30 D1AN Inverting Input D1 for Channel A
33 ADJ Output Level Adjust
34
SEL
Mux Select Input. SEL is internally
pulled down by a 400kI (typ) resistor.
Active-Low Enable Input. EN2 is inter-
37 EN2 nally pulled up by a 400kI (typ)
resistor.
Active-High Enable Input. EN1 is
38 EN1 internally pulled down by a 400kI (typ)
resistor.
— EP Exposed Pad. Connect EP to GND.
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MAX14886.PDF ] | |
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