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PDF FX980 Data sheet ( Hoja de datos )
| Número de pieza | FX980 | |
| Descripción | TETRA Baseband Processor | |
| Fabricantes | CML Microcircuits | |
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CML Semiconductor Products
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TETRA Baseband Processor FX980
1.0 Features
D/980/3 November 1997
Advance Information
• RRC Filters for both Tx and Rx
• π/4 DQPSK Modulation
• 2x 13-Bit Resolution Sigma Delta D-A
• 2x 16-Bit Resolution Sigma Delta A-D
• 4 x10-Bit D-A and 4 Input 10-Bit A-D
• Transmit Output Power Control
• Low Power 3.0 - 5.5Volt Operation
• Effective Power down Modes
1.1 Brief Description
This device is intended to act as an interface between the analogue and digital sections of a Digital Radio
System, and performs many critical and DSP-intensive functions. The chip is designed with the necessary
capability to meet the requirements for use in both mobile and base station applications in Terrestrial Trunked
Radio (TETRA) systems.
The transmit path comprises all the circuitry required to convert digital data into suitably filtered analogue I
and Q signals for subsequent up-conversion and transmission. This includes digital control of the output
amplitudes, digital control of the output offsets and fully programmable digital filters: default coefficients
provide the RRC response required for TETRA.
The receive section accepts differential analogue I and Q signals at baseband and converts these into a
suitably filtered digital form for further processing and data extraction. A facility is provided for digital offset
correction and the digital filters are fully programmable with default coefficients providing the RRC response
required for TETRA.
Auxiliary DAC and ADC functions are included for the control and measurement of the RF section of the radio
system. This may include AFC, AGC, RSSI, or may be used as part of the control system for a Cartesian
Loop.
© 1997 Consumer Microcircuits Limited
1 page  
TETRA Baseband Processor
1.3 Signal List (continued)
FX980
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L6 Package Package
44 PLCC
#
Pin No. Pin No.
Signal
Name
Type
Description
10
AUXDAC1
O/P Auxiliary DAC channel 1
9
AUXDAC2
O/P Auxiliary DAC channel 2
8
AUXDAC3
O/P Auxiliary DAC channel 3
7
AUXDAC4
O/P Auxiliary DAC channel 4
36
35
32
33
34
6
3,21
27,40
28,39
31
5
4,13,22
BIAS1
BIAS2
VCC1
VCC2
VCC3
VDD1
VDD
VSS1
VSS2
VSSB
VSSA
VSS
BI
BI
Power
Power
Power
Power
Power
Ground
Analogue bias level. This pin should be de-
coupled to VSSB.
Analogue bias level. This pin should be de-
coupled to VSSB.
I Channel analogue positive supply rail. This
pin should be de-coupled to VSS1.
Q Channel analogue positive supply rail. This
pin should be de-coupled to VSS2.
Analogue Bias positive supply rail. Levels and
voltages are dependent upon this supply. This
pin should be de-coupled to VSSB.
Auxiliary analogue positive supply rail. This
pin should be de-coupled to VSSA.
Digital positive supply rail. This pin should be
de-coupled to VSS.
I Channel analogue negative supply rail.
Ground Q Channel analogue negative supply rail.
Ground Analogue Bias negative supply rail.
Ground Auxiliary analogue negative supply rail.
Ground Primary digital negative supply rail.
Notes: I/P = Input
O/P = Output
BI = Bi-directional
© 1997 Consumer Microcircuits Limited
5
D/980/3
5 Page 
TETRA Baseband Processor
FX980
Functions performed by the serial interface include:
• Power up or down and optional bypassing of selected blocks
• Setting digital filter coefficients
• Loading ramp up and ramp down increments and burst lengths for Tx
• Loading and transmitting data
• Loading offset correction, gain multiplier and phase adjustment registers
• Enabling/disabling of output via the Rx serial interface
• Vary sampling time for Rx data relative to the symbol (144kHz) clock.
• Loading data into auxiliary DACs
• Initiating conversions using auxiliary ADCs and reading results
• Writing data to, and reading data from, the Waveform Generation SRAM
• Power Ramping time step control
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The three interfaces consist of the following signal pins:
SClk
CmdDat
CmdFS
CmdRdDat
CmdRdFS
RxDat
RxFS
Output
In/Out
Input
Output
Output
Output
Output
Serial Clock pin. This pin is common for all three interfaces.
Command port Data pin. This pin is by default an input, but may be
configured as an open drain bi-directional pin.
Command port Frame Sync pin. This pin is used to mark the first bit in a
serial frame.
Command read port Data pin. This pin only has active data on it in
response to a read command.
Command read port Frame Sync pin. This pin is used to mark the first bit in
a serial frame.
Receive data port Data pin. This pin is only active when the Rx Data path is
active.
Receive data port Frame Sync pin. This pin is used to mark the first bit in
a serial frame.
Note: All Frame Sync strobe signals are actually coincident with the last bit of a dataframe. See
Figures 4 and 5 for further details.
1.5.6.1 Command Interface
A serial command word consists of a 16-bit frame. Each frame is marked by an active Frame Sync
event which precedes the MSB bit. A command word can be either a control word or a transmit data
word.
MSB
R/W
15
14
Address
87
Data
Command Control Serial Word
MSB
1 Tx Data Address U/D 4/1
15 14
10 9 8 7
Tx Data
Command Transmit Data Serial Word
LSB
0
LSB
0
© 1997 Consumer Microcircuits Limited
11
D/980/3
11 Page | ||
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