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PDF FX949 Data sheet ( Hoja de datos )
| Número de pieza | FX949 | |
| Descripción | CDPD Wireless Modem Data Pump | |
| Fabricantes | CML Microcircuits | |
| Logotipo |  |
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CML Semiconductor Products
www.DataSheet4U.com
FX949CDPD Wireless Modem Data Pump
1.0 Features
Obsolete Product
'For Information Only'
• MES Full Duplex Operation
• Forward Channel Decoding
• Reverse Channel Encoding
• Error Detection and Syndrome Output
• 19.2kb/s GMSK Modulation
• Sleep Timer Included
• 3.3V and 5V Applications
• PCMCIA Package Option
1.1 Brief Description
The FX949 is a low power CMOS integrated circuit which performs all of the real-time signal and data
format-management functions required for full-duplex operation of a CDPD Mobile End Station.
The FX949 interfaces directly with the analogue modulation and demodulation circuits of the radio and
the host radio/application processor bus.
It accepts application data from the processor, constructs a correct Reverse Channel packet containing
this data and converts the packet to GMSK analogue signals for transmission. In receive, Forward
Channel GMSK signals from the discriminator are demodulated, the packet disassembled, error
checked, and the recovered application data passed to the processor.
The FX949 is the cost, size, and power efficient alternative to DSP design solutions in high
performance OEM products for the Cellular Digital Packet Data wireless services.
© 1996 Consumer Microcircuits Limited
1 page  
CDPD Wireless Modem Data Pump
FX949
www.DataSheet4U.com
Package Package
L4 L6
Signal
Pin No. Pin No.
Name
Type
33 37 CSN
I/P
34 38 WRN
I/P
35 39 RDN
I/P
38 41 A6
39 42 A5
43 1 A4
44 2 A3
45 3 A2
46 4 A1
47 5 A0
I/P
I/P
I/P
I/P
I/P
I/P
I/P
Description
Chip Select. An active low logic level input to the
modem, used to enable a data read or write
operation.
Write. An active low logic level input used to
control the writing of data into the modem from
the controlling µP.
Read. An active low logic level input used to
control the reading of data from the modem into
the controlling µP.
)
)
)
) 7 logic level modem register address select
) inputs.
)
)
1, 6,
11, 19,
24, 30,
36, 37,
40, 41,
42, 48
21, 22,
23, 25,
28, 29,
31
6, 7,
16, 28,
30, 40,
43, 44
25, 26,
27, 29,
33, 34,
35
)
)
) No internal connection: leave open circuit.
)
)
)
)
) Internally connected: leave open circuit.
)
)
Notes:
I/P = Input
O/P = Output
BI = Bidirectional
© 1996 Consumer Microcircuits Limited
5
D/949/5
5 Page 
CDPD Wireless Modem Data Pump
FX949
Read Only Register Description
www.DataSheet4U.com
RXDATA0 to RXDATA62 Registers (Hex address $00 to $3E)
These are read only registers and all 63 registers are each updated with 6-bit symbols every time a valid SYNC
occurs. This is indicated by an interrupt (see SYNC, SYNC ERRORS, and SYNC ERROR LIMIT).
SYNDROME SYMBOL 1 to 16 (Hex address $3F to $4E)
These 16, 6-bit symbols contain the syndrome calculated from the received data (RXDATA 0 to 62). The
syndrome is recalculated every time a valid SYNC occurs. An all zero pattern in the 16 syndrome symbols
indicates zero errors in the data.
STATUS Register (Hex address $4F)
This is a read only register that contains the status of the various functions on the device as described below:
SYNC
(Bit 7)
This bit is set to "1" when a forward channel synchronisation word has been
received successfully. (See SYNC ERRORS and SYNC ERROR LIMIT). This bit is
reset to "0" when the sync word has not been detected for more than 420 bits (i.e.
sync lost).
DEC
(Bit 6)
This bit indicates the decode status of the Mobile Data Base Station (MDBS) on the
forward channel. This bit is set to "1" when the station fails to decode data
successfully, and is reset to "0" when the station is successful in decoding data.
This bit will only change and be valid if SYNC (Bit 7) is set to "1".
IDLE
(Bit 5)
This bit indicates the active status of the Mobile Data Base Station (MDBS) on the
forward channel. This bit is set to "0" when the station is in an IDLE state, and reset
to "1" when the station is in a BUSY state. This bit will only change and be valid if
SYNC (Bit 7) is set to "1".
The IDLE bit is derived from a majority decision on the five consecutive busy/idle
bits, as in the CDPD specification.
The first block of data received in the forward channel will not output any data until
the sync word has been found. Once this has been found, the most recent (last) idle
bit will be output in the STATUS register, and the IDLEF bit will be set to "1" in the
IRQ FLAGS register.
The next seven idle bits are output as they come in and, so long as the sync word
remains correct, successive idle bits are output as they come in.
ERROR
(Bit 4)
This bit indicates if there are errors in RXDATA. This bit is set to "0" if all syndrome
symbols (1 - 16) are "0", i.e. no errors in the data. This bit is set to "1" if any
syndrome symbol is not "0", i.e. errors are present in the data. This bit is updated
every time a valid SYNC occurs.
SYNC ERRORS
(Bits 2, 1 and 0)
This 3-bit number indicates the number of errors received in the synchronisation
word. It is updated whenever the synchronisation word is in error less than or equal
to the number specified by the SYNC ERROR LIMIT bits of the CONTROL register.
It also implies the synchronisation word has been received successfully and sets the
SYNC bit to "1" (See SYNC above).
© 1996 Consumer Microcircuits Limited
11
D/949/5
11 Page | ||
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