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PDF 25LC040A Data sheet ( Hoja de datos )
| Número de pieza | 25LC040A | |
| Descripción | (25LC0x0A) 1K-4K SPI Serial EEPROM High Temp Family Data Sheet | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 25LC040A (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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25LC010A
25LC020A
25LC040A
1K-4K SPI Serial EEPROM High Temp Family Data Sheet
Features:
• Max. Clock 5 MHz
• Low-Power CMOS Technology:
- Max. Write Current: 5 mA at 5.5V, 5 MHz
- Read Current: 5 mA at 5.5V, 5 MHz
- Standby Current: 10 μA at 5.5V
• 128 x 8 through 512 x 8-bit Organization
• Byte and Page-level Write Operations
• Self-Timed Erase and Write Cycles (6 ms max.)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential Read
• High Reliability:
- Endurance: >1M erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature Range Supported:
- Extended (H):
-40°C to +150°C
• Package is Pb-Free and RoHS Compliant
Pin Function Table
Name
Function
CS Chip Select Input
SO Serial Data Output
WP Write-Protect
VSS Ground
SI Serial Data Input
SCK
HOLD
VCC
Serial Clock Input
Hold Input
Supply Voltage
Description:
Microchip Technology Inc. 25LCXXXA* devices are
low-density 1 through 4 Kbit Serial Electrically Eras-
able PROMs (EEPROM). The devices are organized in
blocks of x8-bit memory and support the Serial Periph-
eral Interface (SPI) compatible serial bus architecture.
Byte-level and page-level functions are supported.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25LCXXXA is available in a standard 8-lead SOIC
package. The package is Pb-free and RoHS
Compliant.
Package Types (not to scale)
SOIC
(SN)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
*25LCXXXA is used in this document as a generic part number for the 25 series devices.
© 2009 Microchip Technology Inc.
www.DataSheet.in
Preliminary
DS22136B-page 1
1 page  
TABLE 1-3: AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
—
VHI = VCC - 0.2V
(Note 1)
VHI = 4.0V
(Note 2)
CL = 50 pF
—
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
25LCXXXA
© 2009 Microchip Technology Inc.
www.DataSheet.in
Preliminary
DS22136B-page 5
5 Page 
25LCXXXA
3.4 Write Enable (WREN) and Write
Disable (WRDI)
The 25LCXXXA contains a write enable latch. See
Table 5-1 for the write-protect functionality matrix. This
latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
• WP pin is brought low
FIGURE 3-4:
WRITE ENABLE SEQUENCE (WREN)
CS
SCK
01234567
FIGURE 3-5:
SI 0 0 0 0 0 1 1 0
High-Impedance
SO
WRITE DISABLE SEQUENCE (WRDI)
CS
SCK
01234567
SI 0 0 0 0 0 1 10 0
High-Impedance
SO
© 2009 Microchip Technology Inc.
www.DataSheet.in
Preliminary
DS22136B-page 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 25LC040A.PDF ] | |
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