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PDF EP5388QI Data sheet ( Hoja de datos )

Número de pieza EP5388QI
Descripción 800mA Synchronous Buck Regulator
Fabricantes Enpirion 
Logotipo Enpirion Logotipo



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Product Overview
The EP5388QI is a synchronous buck
converter with integrated Inductor, PWM
controller, MOSFETS, and Compensation
providing the smallest possible solution size.
The EP5388QI requires only two small MLCC
capacitors to make a complete solution.
Integration of the inductor greatly simplifies
design, contains noise, reduces part count, and
reduces solution footprint. Low output ripple
ensures compatibility with RF systems.
The EP5388QI operates at a switching
frequency of 4 MHz, enabling this
unprecedented level of integration and small
external components. Type III voltage mode
control is used to provide high noise immunity
and wide control loop bandwidth.
The small footprint makes this part ideal for
space constrained portable applications.
Shutdown current of <1uA extends battery life
Output voltage level is programmed via a 3-pin
VID selector providing seven pre-programmed
output voltages along with an option for
external resistor divider.
Applications
Noise Sensitive RF Applications
Area Constrained Applications
Wireless Data Applications
Portable Gaming Devices
Personal Media Players
Advanced Mobile Processors, DSP, IO,
Memory, Video, Multimedia Engines
Ordering Information
Part Number
EP5388QI-T
EP5388QI-E
Temp Rating (°C)
Package
-40 to +85
16-pin QFN T&R
EP5388QI Evaluation Board
EP5388QI
800mA Synchronous Buck Regulator
With Integrated Inductor
3mm x 3mm x 1.1mm Package
July 2008
RoHS Compliant
Halogen Free
Product Highlights
Featuring Integrated Inductor Technology
3mm x 3mm x 1.1mm QFN package
Only two low cost MLCC caps required
4 MHz switching frequency
High efficiency, up to 94%
Up to 800mA continuous output current
Wide 2.4V to 5.5V input range
VOUT range 0.6V to VIN – 0.5V
3-Pin VID output voltage programming
100% duty cycle capable
Less than 1 µA standby current
Low VOUT ripple for RF compatibility
Short circuit and over current protection
UVLO and thermal protection
RoHS compliant; MSL 3 260°C reflow
Typical Application Circuit
VIN
4.7µF
0603
Voltage
Select
ENABLE
VSense
Vin Vout
EP5388QI
VFB
VS0
VS1
VS2 GND
VOUT
47uF
1206
Figure 1. Typical application circuit.
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EP5388QI pdf
July 2008
EP5388QI
PARAMETER
SYMBOL
Soft-Start Operation
Soft-Start Slew Rate
Vss
Time to 90% Vout
Tss
† Parameter guaranteed by design.
TEST CONDITIONS
Vout = 3.3V
MIN
1.125
TYP
1.5
2
MAX
1.875
UNITS
V/mS
mS
Typical Performance Characteristics
Typical performance characteristics are measured using the application circuit in Figure 1. All
measurements made at 25ºC.
95 95
90 90
85 85
80 80
75 75
70 70
65 65
60 60
55 55
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
Efficiency, VIN = 3.3V, VOUT = 2.5V,1.8V,1.5V, 1.2V,
top to bottom.
Efficiency, VIN = 3.7V, VOUT = 2.5V,1.8V,1.5V, 1.2V,
top to bottom.
95
90
85
80
75
70
65
60
55
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80
Load Current (A)
Efficiency, VIN = 5V, VOUT = 3.3V, 2.5V,1.8V,1.5V, 1.2V,
top to bottom.
Output Ripple, VIN = 5V, VOUT = 1.2V; Load = 500mA.
©Enpirion 2008 all rights reserved, E&OE
www.DataSheet.in
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EP5388QI arduino
July 2008
EP5388QI
Recommendation 4: Multiple small vias (approximately 0.25mm finished diameter) should be used
to connect the ground terminals of the input and output capacitors, and the surface ground pour
under the device, to the system ground plane. If a local ground island is used on PCB layer 2, the
vias should connect to the ground island and continue down to the PCB system ground plane.
Recommendation 5: The AGND pin should be connected to the system ground plane using a via as
described in recommendation 4. AGND must NOT be connected to the surface layer ground pour.
Recommendation 6: As with any switch-mode DC-DC converter, do not run any sensitive signal or
control lines under the converter package.
Vias Slit
Figure 6. PCB layout recommendation.
Recommended PCB Footprint
©Enpirion 2008 all rights reserved, E&OE
www.DataSheet.in
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