PDF UT62L5128 Data sheet ( Hoja de datos )

Número de pieza	UT62L5128
Descripción	512K X 8 BIT LOW POWER CMOS SRAM
Fabricantes	Utron technology
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No Preview Available !  Rev. 1.4 UTRON REVISION HISTORY UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM REVISION Preliminary Rev. 0.5 Rev. 1.0 DESCRIPTION Released DATE Original. Mar, 2001 1. The symbols CE# and OE# and WE# are revised as. CE and Jun 21,2001 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 OE and WE . 2. Separate Industrial and Consumer SPEC. 3. Add access time 55ns range. Add STSOP package Add SOP package 1. Revised 36-pin TFBGA package outline dimension a Rev. 1.2 : ball diameter=0.3mm b Rev. 1.3 : ball diameter=0.35mm 2. Revised DC ELECTRICAL CHARACTERISTICS c Revised VIH as 2.2V 1. Revised Operation surrent : -Icc(max) 45/35/25mA 40/30/25mA -Icc(Typ) 30/25/20mA 30/20/16mA 2. Revised Standby current : 20/3uA 20/2uA 3. Revised VOH(Typ) : NA 2.7V 4. Add VIH(max)=VCC+2.0V for pulse width less than 10ns. VIL(min)=VSS-2.0V for pulse width less than 10ns. 5. Revised AC Table tOHZ* characteristics 6. Add order information for lead free product Aug 3,2001 Mar 25,2002 May 3,2002 May 8,2003 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 www.DataSheet.in P80051 1 page  Rev. 1.4 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM CAPACITANCE (TA=25 , f=1.0MHz) PARAMETER SYMBOL MIN. Input Capacitance CIN - Input/Output Capacitance CI/O - Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS MAX 6 8 UNIT pF pF Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF+1TTL, IOH/IOL = -1mA/2.1mA AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA =0 to 70 / -20 to 80 (E)) (1) READ CYCLE PARAMETER SYMBOL Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH UT62L5128-55 MIN. MAX. 55 - - 55 - 55 - 30 10 - 5- - 20 - 20 10 - UT62L5128-70 MIN. MAX. 70 - - 70 - 70 - 35 10 - 5- - 25 - 25 10 - UT62L5128-100 MIN. MAX. 100 - - 100 - 100 - 50 10 - 5- - 30 - 30 10 - UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER SYMBOL UT62L5128-55 MIN. MAX. UT62L5128-70 MIN. MAX. Write Cycle Time tWC 55 - 70 - Address Valid to End of Write tAW 50 - 60 - Chip Enable to End of Write tCW 50 - 60 - Address Set-up Time tAS 0 - 0 - Write Pulse Width tWP 45 - 55 - Write Recovery Time tWR 0 - 0 - Data to Write Time Overlap tDW 25 - 30 - Data Hold from End of Write Time tDH 0 -0 - Output Active from End of Write tOW* 5 - 5 - Write to Output in High Z tWHZ* - 30 - 30 *These parameters are guaranteed by device characterization, but not production tested. UT62L5128-100 MIN. MAX. 100 - 80 - 80 - 0- 70 - 0- 40 - 0- 5- - 40 UNIT ns ns ns ns ns ns ns ns ns ns UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 www.DataSheet.in P80051 5 Page  Rev. 1.4 UTRON UT62L5128 512K X 8 BIT LOW POWER CMOS SRAM 32-pin 8mm x 20mm TSOP- Package Outline Dimension HD CL 1 32 16 17 "A" Seating Plane y D 16 17 GAUGE PLANE SEATING PLANE 1 32 "A" DETAIL VIEW L1 UNIT SYMBOL A A1 A2 b D E e HD L1 y INCH(BASE) 0.047 (MAX) 0.004 0.002 0.039 0.002 0.008 + 0.002 - 0.001 0.724 0.004 0.315 0.004 0.020 (TYP) 0.787 0.008 0.0315 0.004 0.003 (MAX) 0o 5o MM(REF) 1.20 (MAX) 0.10 0.05 1.00 0.05 0.20 + 0.05 -0.03 18.40 0.10 8.00 0.10 0.50 (TYP) 20.00 0.20 0.80 0.10 0.076 (MAX) 0o 5o UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 www.DataSheet.in P80051 11 Page

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