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PDF HY27UF161G2A Data sheet ( Hoja de datos )
| Número de pieza | HY27UF161G2A | |
| Descripción | 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY27UF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1Gb NAND FLASH
HY27UF081G2A
HY27UF161G2A
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.4 / Jun. 2007
1
www.DataSheet.in
1 page  
HY27UF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
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Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Input / Outputs (x16 only)
Data Inputs / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1: Signal Names
Rev 0.4 / Jun. 2007
5
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5 Page 
HY27UF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must
be high. See figure 6 and table 13 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. To insert the 28 addresses needed to access
the 1Gbit 4 clock cycles (x8 version) are needed. Addresses are accepted with Chip Enable low, Address Latch Enable
High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for
commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 7 and table 16
for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration
(X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure
8 and table 13 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 9,10,12,13 and table 13 for
details of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.4 / Jun. 2007
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