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PDF LM26001B Data sheet ( Hoja de datos )
| Número de pieza | LM26001B | |
| Descripción | 1.5A Switching Regulator | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 29, 2008
LM26001B
1.5A Switching Regulator with High Efficiency Sleep Mode
General Description
The LM26001B is a switching regulator designed for the high
efficiency requirements of applications with stand-by modes.
The device features a low-current sleep mode to maintain ef-
ficiency under light-load conditions and current-mode control
for accurate regulation over a wide input voltage range. Qui-
escent current is reduced to 10 µA typically in shutdown mode
and less than 40 µA in sleep mode. Forced PWM mode is also
available to disable sleep mode.
The LM26001B can deliver up to 1.5A of continuous load cur-
rent with a fixed current limit, through the internal N-channel
switch. The part has a wide input voltage range of 4.0V to 18V
and can operate with input voltages as low as 3V during line
transients.
Operating frequency is adjustable from 150 kHz to 500 kHz
with a single resistor and can be synchronized to an external
clock.
Other features include Power good, adjustable soft-start, en-
able pin, input under-voltage protection, and an internal boot-
strap diode for reduced component count.
Features
■ High efficiency sleep mode
■ 40 µA typical Iq in sleep mode
■ 10 µA typical Iq in shutdown mode
■ 3.0V minimum input voltage
■ 4.0V to 18V continuous input range
■ 2.0% reference accuracy
■ Cycle-by-cycle current limit
■ Adjustable Frequency (150 kHz to 500 kHz)
■ Synchronizable to an external clock
■ Power Good Flag
■ Forced PWM function
■ Adjustable Soft-start
■ TSSOP-16 exposed pad package
■ Thermal Shut Down
Applications
■ Automotive Telematics
■ Navigation systems
■ In-Dash Instrumentation
■ Battery Powered Applications
■ Stand-by power for home gateways/set-top boxes
Typical Application Circuit
© 2008 National Semiconductor Corporation 300019
www.DataSheet.in
30001901
www.national.com
1 page  
Typical Performance Characteristics Unless otherwise specified the following conditions apply: Vin =
12V, TJ = 25°C.
VFB vs Temperature
VFB vs Vin
(IDC = 300 mA)
30001903
IQ and IVBIAS vs Temperature (Sleep Mode)
30001905
IQ and IVBIAS vs Temperature (PWM Mode)
30001904
Normalized Switching Frequency vs Temperature (300kHz)
30001906
UVLO Threshold vs Temperature (VDD = VIN)
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30001916
5
30001917
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5 Page 
FREQUENCY ADJUSTMENT AND SYNCHRONIZATION
The switching frequency of the LM26001B can be adjusted
between 150 kHz and 500 kHz using a single external resis-
tor. This resistor is connected from the FREQ pin to ground
as shown in the typical application. The resistor value can be
calculated with the following empirically derived equation:
RFREQ = (6.25 x 1010) x fSW-1.042
For most applications where 3V < Vout < 10V, VBIAS can be
connected to Vout. If not used, VBIAS should be tied to GND.
If VBIAS drops below 2.9V (typical), the device automatically
switches over to supply the internal bias voltage from Vin.
Total device input current is the sum of Iq, gate drive current,
and VBIAS current, plus some negligible current into the FB
pin. Total minimum input supply current can be calculated as
shown below:
30001951
FIGURE 5. Swtiching Frequency vs RFREQ
The switching frequency can also be synchronized to an ex-
ternal clock signal using the SYNC pin. The SYNC pin allows
the operating frequency to be varied above and below the
nominal frequency setting. The adjustment range is from 30%
above nominal to 20% below nominal. External synchroniza-
tion requires a 1.2V (typical) peak signal level at the SYNC
pin. The FREQ resistor must always be connected to initialize
the nominal operating frequency. The operating frequency is
synchronized to the falling edge of the SYNC input. When
SYNC goes low, the high-side switch turns on. This allows
any duty cycle to be used for the sync signal when synchro-
nizing to a frequency higher than nominal. When synchroniz-
ing to a lower frequency, however, there is a minimum duty
cycle requirement for the SYNC signal, given in the equation
below:
Where IQG is the gate drive current, calculated as:
IQG = (4.6 x 10-9) x fSW
Total supply input current varies according to load, system
efficiency, and operating frequency. To calculate minimum
input current during sleep mode, use Iq_Sleep_VB, and
IBIAS_SLEEP.
For input current in PWM mode, use the same equation, with
Iq_PWM_VB, and IBIAS_PWM.
If VBIAS is connected to ground, use the same equation with
the Ibias term eliminated and either Iq_Sleep_VDD or
Iq_PWM_VDD.
LOW VIN OPERATION AND UVLO
The LM26001B is designed to remain operational during short
line transients when input voltage may drop as low as 3.0V.
Minimum nominal operating input voltage is 4.0V. Below this
voltage, switch RDS(ON) increases, due to the lower gate drive
voltage from VDD. The minimum voltage required at VDD is
approximately 3.5V for normal operation within specification.
VDD can also be used as a pull-up voltage for functions such
as PGOOD and FPWM. Note that if VDD is used externally,
the pin is not recommended for loads greater than 1 mA.
If the input voltage approaches the nominal output voltage,
the duty cycle is maximized to hold up the output voltage. In
this mode of operation, once the duty cycle reaches its max-
imum, the LM26001B can skip a maximum of seven off puls-
es, effectively increasing the duty cycle and thus minimizing
the dropout from input to output. Typical off-pulse skipping
waveforms are shown below.
Where fnom is the nominal switching frequency set by the
FREQ resistor, and fsync is a square wave. If the SYNC pin
is not used, it must be pulled low for normal operation. A
10kΩ pull-down resistor is recommended to protect against a
missing sync signal. Although the LM26001B is designed to
operate at up to 500 kHz, maximum load current may be lim-
ited at higher frequencies due to increased temperature rise.
See the Thermal Considerations section.
VBIAS
The VBIAS pin is used to bypass the internal regulator which
provides the bias voltage to the LM26001B. When the VBIAS
pin is connected to a voltage greater than 3V, the internal
regulator automatically switches over to the VBIAS input. This
reduces the current into VIN (Iq) and increases system effi-
ciency. Using the VBIAS pin has the added benefit of reducing
power dissipation within the device.
30001929
FIGURE 6. Off-pulse Skipping Waveforms
Vin = 3.5V, Vnom = 3.3V, fnom = 305kHz
UVLO is sensed at both VIN and VDD, and is activated when
either voltage falls below 2.9V (typical). Although VDD is typ-
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet LM26001B.PDF ] | |
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