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PDF SC16C852L Data sheet ( Hoja de datos )
| Número de pieza | SC16C852L | |
| Descripción | 16 mode or 68 mode bus interface | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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SC16C852L
1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared
(IrDA) and 16 mode or 68 mode bus interface
Rev. 03 — 18 January 2008
Product data sheet
1. General description
The SC16C852L is a 1.8 V, low power, dual channel Universal Asynchronous Receiver
and Transmitter (UART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. The SC16C852L is pin compatible with the SC16C652B. SC16C852L
can be programmed to operate in extended mode (see Section 6.2) where additional
advanced UART features are available. The SC16C852L UART provides enhanced UART
functions with 128-byte FIFOs, modem control interface, DMA mode data transfer, and
IrDA encoder/decoder. The DMA mode data transfer is controlled by the FIFO trigger
levels and the TXRDY and RXRDY signals. On-board status registers provide the user
with error indications and operational status. System interrupts and modem control
features may be tailored by software to meet specific user requirements. An internal
loopback capability allows on-board diagnostics. Independent programmable baud rate
generators are provided to select transmit and receive baud rates.
The SC16C852L with Intel (16 mode) or Motorola (68 mode) bus host interface operates
at 1.8 V and is available in plastic LQFP48, TFBGA36 and very small (Micro-UART)
HVQFN32 packages.
2. Features
I Dual channel high performance UART
I Intel or Motorola bus interface selectable using 16/68 pin
I 1.8 V operation
I Up to 5 Mbit/s data rate
I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
I 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
I 128 programmable Receive and Transmit FIFO interrupt trigger levels
I 128 Receive and Transmit FIFO reporting levels (level counters)
I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control
I Industrial temperature range (−40 °C to +85 °C)
I Pin, function, and software compatible to SC16C652B in LQFP48 package
I 128 hardware and software trigger levels
I Automatic 9-bit mode (RS-485) address detection
I Automatic RS-485 driver turn-around with programmable delay
I Dual channel concurrent write
I UART software reset
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1 page  
NXP Semiconductors
5. Pinning information
5.1 Pinning
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
terminal 1
index area
D6
D7
RXB
RXA
TXA
TXB
CSA
CSB
1
2
3
4
5
6
7
8
SC16C852LIBS
(16 mode)
24 RESET
23 RTSA
22 INTA
21 INTB
20 A0
19 A1
18 A2
17 16
a. 16 mode
Transparent top view
002aac179
terminal 1
index area
D6
D7
RXB
RXA
TXA
TXB
CS
A3
1
2
3
4
5
6
7
8
SC16C852LIBS
(68 mode)
24 RESET
23 RTSA
22 IRQ
21 n.c.
20 A0
19 A1
18 A2
17 68
Transparent top view
b. 68 mode
Fig 3. Pin configuration for HVQFN32
002aac629
SC16C852L_3
Product data sheet
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Rev. 03 — 18 January 2008
© NXP B.V. 2008. All rights reserved.
5 of 63
5 Page 
NXP Semiconductors
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Table 2. Pin description …continued
Symbol Pin
Type Description
LQFP48 HVQFN32 TFBGA36
LOWPWR 12
9
D3 I Low Power. When asserted (active HIGH), the device immediately
goes into low power mode. The oscillator is shut-off and some host
interface pins are isolated from the host’s bus to reduce power
consumption. The device only returns to normal mode when the
LOWPWR pin is de-asserted. On the negative edge of a
de-asserting LOWPWR signal, the device is automatically reset
and all registers return to their default reset states. This pin has an
internal pull-down resistor, therefore, it can be left unconnected.
16/68
24
17
F6
I Bus select. Intel or Motorola bus select.
When 16/68 pin is at logic 1 or left unconnected (internally
pulled-up) the device will operate in Intel bus type of interface.
When 16/68 pin is at logic 0, the device will operate in Motorola
bus type of interface.
n.c. 25, 37 -
A4, B4,
B5, E4
-
not connected
[1] HVQFN32 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
6. Functional description
The SC16C852L provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufactured on a single integrated silicon chip. The SC16C852L represents such
an integration with greatly enhanced features. The SC16C852L is fabricated with an
advanced CMOS process.
The SC16C852L is an upward solution to the SC16C652B that provides a dual UART
capability with 128 bytes of transmit and receive FIFO memory, instead of 32 bytes for the
SC16C652 and 16 bytes in the SC16C2550. The SC16C852L is designed to work with
high speed modems and shared network environments that require fast data processing
time. Increased performance is realized in the SC16C852L by the transmit and receive
FIFOs. This allows the external processor to handle more networking tasks within a given
time. In addition, the four selectable receive and transmit FIFO trigger interrupt levels are
provided in SC16C652 mode, or 128 programmable levels are provided in the extended
mode for maximum data throughput performance especially when operating in a
multi-channel environment (see Section 6.2 “Extended mode (128-byte FIFO)”). The FIFO
memory greatly reduces the bandwidth requirement of the external controlling CPU and
increases performance. A low power pin (LOWPWR) is provided to further reduce power
consumption by isolating the host bus interface.
SC16C852L_3
Product data sheet
Rev. 03 — 18 January 2008
© NXP B.V. 2008. All rights reserved.
11 of 63
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