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PDF LTC6994-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC6994-1 | |
| Descripción | Delay Block / Debouncer | |
| Fabricantes | Linear Technology Corporation | |
| Logotipo |  |
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Features
n Delay Range: 1µs to 33.6 Seconds
n Configured with 1 to 3 Resistors
n Delay Max Error:
– <2.3% for Delay > 512µs
– <3.4% for Delay of 8µs to 512µs
– <5.1% for Delay of 1µs to 8µs
n Delay One or Both Rising/Falling Edges
n 2.25V to 5.5V Single Supply Operation
n 70µA Supply Current at 10µs Delay
n 500µs Start-Up Time
n CMOS Output Driver Sources/Sinks 20mA
n –40°C to 125°C Operating Temperature Range
n Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN
Applications
n Noise Discriminators/Pulse Qualifiers
n Delay Matching
n Switch Debouncing
n High Vibration, High Acceleration Environments
n Portable and Battery-Powered Equipment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
Electrical Specifications Subject to Change
LTC6994-1/LTC6994-2
TimerBlox: Delay Block/
Debouncer
Description
The LTC®6994 is a programmable delay block with a
range of 1µs to 33.6 seconds. The LTC6994 is part of the
TimerBlox™ family of versatile silicon timing devices.
A single resistor, RSET , programs the LTC6994’s internal
master oscillator frequency. The input-to-output delay
is determined by this master oscillator and an internal
clock divider,
1 to 221:
NDIV ,
programmable
to
eight
settings
from
tDELAY
=
NDIV •RSET
50kΩ
• 1µs,
NDIV
=
1, 8,
64,...,221
The output (OUT) follows the input (IN) after delaying the
rising and/or falling transitions. The LTC6994-1 will delay
the rising or falling edge. The LTC6994-2 will delay both
transitions, and adds the option to invert the output.
DEVICE
DELAY FUNCTION
LTC6994-1
or
LTC6994-2
or
The LTC6994 also offers the ability to dynamically adjust the
width of the output pulse via a separate control voltage.
The LTC6994 is available in the 6-lead SOT-23 (ThinSOT)
and 6-lead 2mm × 3mm DFN packages.
Typical Application
Noise Discriminator
NOISY
INPUT
IN OUT
LTC6994-2
GND V+
QUALIFIED
OUTPUT
3.3V
0.1µF
SET
RSET
75k
DIV
699412 TA01a
IN
2V/DIV
OUT
2V/DIV
1.5µs
1.5µs
20µs/DIV
699412 TA01b
699412p
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LTC6994-1/LTC6994-2
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Delay Error vs Temperature
(NDIV = 1)
Delay Error vs Temperature
(NDIV = 1)
Delay Error vs Temperature
(NDIV = 1)
Delay Error vs Temperature
(8 ≤ NDIV ≤ 64)
Delay Error vs Temperature
(8 ≤ NDIV ≤ 64)
Delay Error vs Temperature
(8 ≤ NDIV ≤ 64)
Delay Error vs Temperature
(NDIV ≥ 512)
Delay Error vs Temperature
(NDIV ≥ 512)
Delay Error vs Temperature
(NDIV ≥ 512)
699412p
5 Page 
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LTC6994-1/LTC6994-2
Operation
The LTC6994 is built around a master oscillator with a 1µs
minimum period. The oscillator is controlled by the SET
pin current (ISET) and voltage (VSET), with a 1µs/50kΩ
conversion factor that is accurate to ±1.7% under typical
conditions.
tMASTER
=
1µs
50kΩ
•
VSET
ISET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the input-to-output
delay. The simplest way to generate ISET is to connect a
resistor (RSET) between SET and GND, such that ISET =
VSET/RSET . The master oscillator equation reduces to:
tMASTER
=
1µs
•
RSET
50kΩ
From this equation, it is clear that VSET drift will not affect
the input-to-output delay when using a single program
resistor (RSET). Error sources are limited to RSET tolerance
and the inherent accuracy ∆tDELAY of the LTC6994.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25µA and 20µA).
When the input makes a transition that will be delayed
(as determined by the part version and POL bit setting),
the master oscillator is enabled to time the delay. When
the desired duration is reached, the output is allowed to
transition.
The LTC6994 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
512, 4096, 215, 218 or 221. This extends the delay duration
by those same factors. The divider ratio NDIV is set by a
resistor divider attached to the DIV pin.
tDELAY
=
NDIV
50kΩ
•
VSET
ISET
• 1µs
With RSET in place of VSET/ISET the equation reduces to:
tDELAY
=
NDIV •RSET
50kΩ
• 1µs
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit A/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6994:
1. DIVCODE determines the output frequency divider set-
ting, NDIV .
2. The DIVCODE MSB is the POL bit, and configures a
different polarity setting on the two versions.
a. LTC6994-1: POL selects rising or falling-edge delays.
POL = 0 will delay rising-edge transitions. POL = 1
will delay falling-edge transitions.
b. LTC6994-2: POL selects the output inversion.
POL = 1 inverts the output signal.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
2.25V TO 5.5V
V+
LTC6994
R1
DIV
R2
GND
699412 F01
Figure 1. Simple Technique for Setting DIVCODE
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIV and POL values for the recommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects)
2. The driving impedance (R1||R2) does not exceed
500kΩ.
699412p
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| PDF Descargar | [ Datasheet LTC6994-1.PDF ] | |
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