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PDF LTC6991 Data sheet ( Hoja de datos )
| Número de pieza | LTC6991 | |
| Descripción | Resettable Low Frequency Oscillator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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DataSheet.in
Features
n Period Range: 1ms to 9.5 Hours
n Configured with 1 to 3 Resistors
n <1.5% Maximum Frequency Error
n Output Reset Function
n 2.25V to 5.5V Single Supply Operation
n 55µA to 80µA Supply Current
(2ms to 9.5hr Clock Period)
n 500µs Start-Up Time
n CMOS Output Driver Sources/Sinks 20mA
n –40°C to 125°C Operating Temperature Range
n Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN Packages
Applications
n “Heartbeat” Timers
n Watchdog Timers
n Intervalometers
n Periodic “Wake-Up” Call
n High Vibration, High Acceleration Environments
n Portable and Battery-Powered Equipment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT and TimerBlox are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
Electrical Specifications Subject to Change
LTC6991
TimerBlox: Resettable Low
Frequency Oscillator
Description
The LTC®6991 is a silicon oscillator with a programmable
period range of 1.024ms to 9.54 hours (29.1µHz to 977Hz),
specifically intended for long duration timing events. The
LTC6991 is part of the TimerBlox™ family of versatile
silicon timing devices.
A single resistor, RSET , programs the LTC6991’s internal
master oscillator frequency. The output clock period
is determined by this master oscillator and an internal
frequency divider,
from 1 to 221.
NDIV ,
programmable
to
eight
settings
tOUT
=
NDIV •RSET
50kΩ
• 1.024ms,
NDIV
=
1,8,64,...,221
In normal operation, the LTC6991 oscillates with a 50%
duty cycle. A reset function is provided to truncate the
pulse (reducing the duty cycle). The reset pin can also be
used to prevent the output from oscillating.
The RST and OUT pins can be configured for active-low
or active-high operation using a polarity function.
POL BIT
0
0
1
1
RST PIN
0
1
0
1
OUTPUT STATE
Oscillating
0 (reset)
1 (reset)
Oscillating
The LTC6991 is available in the 6-lead SOT-23 (ThinSOT)
package or a 6-lead 2mm × 3mm DFN.
Typical Application
Low Frequency Pulse Generator
RPW
2.26k
CPW
470pF
RSET
715k
RST OUT
LTC6991
GND V+
SET DIV
tPULSE ≈ RPW • CPW ≈ 1µs
OUT
1µs PULSE WIDTH
60 SECONDS
2.25V TO 5.5V
R1
1M
R2
392k
0.1µF
6991 TA01a
Clock Period Range over Eight Divider Settings
10Hr
1Hr
10Min
1Min
10Sec
1Sec
100ms
10ms
1ms
0
0.625 1.25 1.875
2.5
DIV PIN VOLTAGE, VDIV (V) 6991 TA01b
6991p
1 page  
DataSheet.in
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
LTC6991
Frequency Error vs Temperature
3
GUARANTEED MAX OVER TEMPERATURE
2
RSET = 50k
3 PARTS
1
0
–1
–2 GUARANTEED MIN OVER TEMPERATURE
–3
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
6991 G01
Frequency Error vs RSET
3
GUARANTEED MAX OVER TEMPERATURE
2
3 PARTS
1
0
–1
–2 GUARANTEED MIN OVER TEMPERATURE
–3
0
200 400
600
RSET (kΩ)
800
6991 G04
VSET Drift vs ISET
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
REFERENCED TO ISET = 10µA
5 10 15
ISET (µA)
20
6992 G07
Frequency Error vs Temperature
3
GUARANTEED MAX OVER TEMPERATURE
2
RSET = 200k
3 PARTS
1
0
–1
–2 GUARANTEED MIN OVER TEMPERATURE
–3
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
6991 G02
Frequency Drift vs Supply Voltage
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
2
REFERENCED TO V+ = 4.5V
RSET = 50k
RSET = 200k
RSET = 800k
345
SUPPLY VOLTAGE (V)
6
6991 G05
VSET Drift vs Supply
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
2
REFERENCED TO V+ = 4V
34
SUPPLY (V)
5
6
6991 G08
Frequency Error vs Temperature
3
GUARANTEED MAX OVER TEMPERATURE
2
RSET = 800k
3 PARTS
1
0
–1
–2 GUARANTEED MIN OVER TEMPERATURE
–3
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
6991 G03
Typical VSET Distribution
250
2 LOTS
DFN AND SOT-23
200 1274 UNITS
150
100
50
0
0.98
0.988
0.996 1.004
VSET (V)
1.012 1.02
6991 G06
VSET vs Temperature
1.020 3 PARTS
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
6991 G09
6991p
5 Page 
DataSheet.in
LTC6991
Operation
RST Pin and Polarity (POL) Bit
The RST pin controls the state of the LTC6991’s output
as seen on the OUT pin. The active/inactive voltage levels
depend on the POL bit setting.
Table 2. Output States
POL BIT
0
0
1
1
RST PIN
0
1
0
1
OUTPUT STATE
Oscillating
0 (reset)
1 (reset)
Oscillating
Each period of the LTC6991’s internal oscillator clocks the
output state latch (see Block Diagram). The reset pin (RST)
can reset or hold off the output latch. The active state of
the reset pin is determined by the polarity function (POL).
Similarly, the output latch is followed by a buffer that can
invert the output. The output polarity is also controlled
by the POL bit.
If POL = 0, the reset pin is active high and the output latch
is not inverted. Therefore, pulling the RST pin high will
reset the output latch and force the OUT pin low. Pulling
RST low will allow the output to oscillate, with the next
rising edge dependent on the internal oscillator.
If POL = 1, the reset pin is active low and the output latch
is inverted. Therefore, pulling the RST pin low will reset
the output latch and force the OUT pin high. Pulling RST
high will allow the output to oscillate, with the next falling
edge dependent on the internal oscillator.
Note that the master oscillator frequency and phase are
not affected by the RST pin; The LTC6991 continues to
oscillate, internally, even when RST is active. While the
reset function can block an output pulse, its exact place-
ment in time can only be changed by power cycling the
LTC6991.
tWIDTH
RST
tRST
OUT
tOUT
Figure 3. RST Timing Diagram (POL = 0)
INTERNAL
OSCILLATOR
6991 F03
RST
OUT
tOUT
tRST
INTERNAL
OSCILLATOR
Figure 4. RST Timing Diagram (POL = 1)
6991 F04
6991p
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC6991.PDF ] | |
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