|
|
PDF INS8154 Data sheet ( Hoja de datos )
| Número de pieza | INS8154 | |
| Descripción | N-Channel 128-by-8 Bit RAM Input/Output | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de INS8154 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
e~.National
~ Semiconcluctor
~rRIL 1118
e-zn
CD
www.DataSheet4U.c.o..m.
CIl
~
INS&154 N.ChanRel 12&.by.& Bit
RAM Input/Outriit (RAM 1/0)
Z.
m0::r
General Description
Features
~
The RAM Input/Output Chip if'.' LSI device wh/ch
provides random access memor'
Peripheral inter-
facing for microcomputer syste
he RAM portion
contains 1024 bits of static R
anized as 128x8,
The 1/0 portion consists of t
ripheral ports of
eight bits each. Each of the 1/0 im ln the two ports
may be defined as an input or': -output to provide
0 128x8RAM
0 Single +5-volt power s' plV
0 Low power dissipatio
0 Fully static operation
0 Completely TTL com ibl~Î"
-~
C..D..
.~
CD
c::r
maximum flexibility. Each port iv be read from or
written to in a parallel (8-bit b ' (mode. To improve
0 Two 8-bit programma ji '1/0 ports
0 1/0 port A has TRI-S ;J'El!!>capability
'<
ëo
efficiency and simplify programrijing in control-based
applications, a single bit of 1/0 II\' either port may be
Set, cleared or read with a single rrilcTOprocessor instruc-
0 Handshake controls
0 Single bit 1/0 operati
strobed mode of operation
with single instruction
t_U0
-
tion. ,ln addition to basic 1/0, one\of the ports, port A,
may be programmed to operate!1 in several types of
strobed mode with handshake. St(obed mode together
with optional interrupt operation permit both high
0 Reduces system packs cou nt
0 Direct interface with JMP
Independent operatio" f RAM and 1/0
::a
»
i:
speed parallel data transfers and:, interface to a wide
variety of peripherals with no external logic.
The RAM 1/0 is an n-channe! silicon gate device
packaged in a 40-pin dual-in-li". package. It operates
~th a single 5.volt power SUI't,Py and is fully TTL
,c<Jmpatible.
,
INS8154 MICROBUSTM Configuration
"
MICROBUS"TM* comfib, le
"'-0CC-C-.-:t-~»g.:J'.a....
s:
:::
CPU'
GRO~
ADDRESS
BUS
DATA
BUS
CONTRDl
BUS
M
1
~C cs'1'
B MEMR
U
INS8154
PORT BUS
PORT. ,BUS
-0
S MEMW
RUET
INRI
NOTE
Th,INTR.g",,1 be.oma_o.ly
""'.o.nb,,dd,
mod, wh,. 0
do" "0
1. th,
0. hu
*Trademark, National Semlconductor Corp,
197BNotlonal Semiconductor
Corp,
DA,B15M4B/Printad
in U.s.A.
1 page  
Basic Functional Description
~
The RAM 110 performs two separate but important functions in microcomputer systems. The fwirswt wis.DdaattaaShsteoerat4geU.com
provided by the 128 x 8 RAM. The second function is peripheral interfacing provided by the two 8-bit 110 ports. The
ability to program the configuration and operating modes of the 110 ports allows interfacing a microcomputer to a wide
varity of peripherals with minimum external logic. Major functional blocks of the chip are shown in the block diagram;
an operational summary of the chip is provided in figure 1. A description of the chip pinouts and a summary of the
internai chip registers is given below.
(DB7 - DBO) Data Bus Buffers
The data bus buffer is a TR I-ST A TE, bidirectional, 8-bit
buffer that is used to interface the RAM 110 to a micro-
computer data bus. Data, control, and status information
is transmitted to and received from the RAM 110 via the
data bus buffers. Execution of a STORE instruction by
the microprocessor may be used to transmit data and
control information trom the CPU to the RAM 110.
Execution of a LOAD instruction may be used to trans-
mit data and status information trom the RAM 110 to
the CPU.
(CSO and CS1) Chip Select 1nputs
The combination of a low on CSO and a high on CS1
input pins enables communication between the RAM
110 and the microprocessor.
(MilO) Memory 1/0 Select
- ~_I
The state of the MilO input pin determines whether
communication between the CPU and RAM 110 chip
will in~
RAM portion of the RAM 110 or the 110
portion. A high on M/iO selects the RAM while a low
selects the 110.
(NRDS) Read Strobe
NRDS is an active-Iow read strobe. A low on this pin
enables data or status information to be read trom the
RAM 110.
(NWDS) Write Strobe
NWDS is an active-Iow
enables data or contrai
the RAM 110.
write strobe. A low on this pin
information to be written into
(AD6 - ADO) Address Inputs
The address input bus determines where in the RAM 110
communication will take place. When the RAM is
selected, the address bus determines which of the 128
bytes of RAM will be read trom or written into. When
110 is selected, the address determines which 110 or
control register will be enabled for communication with
the CPU. These pins are normally connected to the seven
low address lines of the microprocessor.
RAM
The RAM contained on the RAM 110 chip consists of
1024 bits organized as 128 eight-bit bytes. Since the
RAM is fully static, no refresh or clocks are required.
Data out ,of the RAM is of the same polarity as data in,
and readout
six-transistor
RAM.
is nondestructive. The RAM is a standard
cell similar in design to the 2102A static
(MDR) Mode Definition Register
The Mode Definition Register is an internai control
register that determines the operating mode of port A.
This register is write on/y. If a read operation is per-
formed with the address set to that of the MDR, the
data bus will remain in the high Impedance state.
(PA7 - PAO, PB7 - PBO) Peripheral Ports A and B
The RAM 110 contains two eight bit 110 ports: port A
and port B. Each port consists of an eight-bit output
data latch with buffer and an eight-bit input data latch.
flexibility is provided with the ability to define any
bit -ô1' the two ports either as an input or as an output.
Bit set, clear and read of ail 110 pins are also provided.
Moreover, port A may be aperated in strabed input or
strobed output modes.
Output Definition Registers - ODRA and ODRB
Associated with each port is an output definition regist' {
(ODR). Each ODR is an eight-bit latch that defines
which of the 110 pins in the respective port are to be
used as outputs. ODRA contrais the direction of port
A and ODRB contrais the direction of port B. Both
ODRs are write on/y registers. If a read operation is
performed with the address set to that of an ODR, the
data bus will remain in the high Impedance state.
(lNTR) Interrupt Request
The interrupt request (lNTR) output is an active high
signal used to interrupt the microprocessor when a
strobed mode data transaction has occured. This signal
is active only when port Ais in the strobed mode. INTR
will be set to a low when a master reset is applied (N RST
set low).
(NRST) Master Reset
NRST is the master reset input for the RAM 110 chip.
A low on this pin clears ail registers in the 110 portion
of the chip (MDR, ODRA, ODRB, and the port output
data latches) and places the data bus in the high imped-
ance state independent of any other control strobes.
After a master reset, the 110 ports will both be in the
basic 110 mode and configured as inputs. The master
reset does not change any data previously stored in the
RAM and does not allow data to be written into or read
from the RAM while NRST is low.
5
5 Page 
Initializing Strobed Input - Mode 2
1
Prior to operation, an initialization procedure must be
undertaken. The MDR must have a "1" written into bit
5 and a "0" written into bit 6. The ODRA must have
"Os" written into it to identify the pins in port A which
will function in mode 2. The ODRB must have a "0"
written into PB7 in order to make it an input which will
receive STB trom the peripheral. Also, PB6 must be
defined as an output so that it can drive the 1BF signal.
The remaining six lower bits of ODRB are configured as
needed for the basic input/output transactions occuring
in port B.
TS OUT M
~
07 06 05
MOR
DO Mode 2
10111-1-1-1-1-1-1
07 06
OORE>
DO
ODRA = "Os" at mode 2 pins.
1
Writing to the MDR to define modwe w2wo.DpeartaatiSohneetw4Uill.com
automatically initialize both 1BF and 1NTR in such a
manner that they will be expecting the peripheral to
begin the first 1/0 transaction with a STB strobe, i.e.,
both 1NTR and 1BF will initialize low when the abave
write to the MDR takes place.
Handshake Status
Handshake status control signais IBF and INTR will be
reset by a microprocessor LOAD instruction only if it
is addressed to port A as a byte read. A parallel write or
bit write or bit read to port A will not affect handshake
status. A byte read or write to port B will not affect
handshake status either, since PB6 and PB7 are masked
from byte writes to port B wh en port A is in any of its
strobed modes. It is possible, however, to override IBF
or lE by an appropriate bit write to PB6 or PB7, respec-
tively.
INTERNAl
D~
Mo'
MoO
INPPBU'T
DATA
LATeH
BIT SET PB'
DUPTBP'UT
DATA
lATeH
IIEI
BITClEAR PB'
00
11IIIJJIJ:..
DEFINITIDN
REGISTER
"'INPUPTIN
(STBI
HANDSHAKE
lDGle
DD
INTERRUPT
REDUEST
lATeH
INTR
DUTPUT PIN
BITSET
PB6
PB6
INPUT
DATA
lATCH
PB6
DUTPUT PIN
(lBF)
BIT CLEAR
./
PB6
DD
DUTPUT
DEFINITIDN
REGISTER
Figure 10. Strobed Input: Mode 2 Handshake Logic
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet INS8154.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| INS8154 | N-Channel 128-by-8 Bit RAM Input/Output | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |