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PDF EDS2532EESL-75 Data sheet ( Hoja de datos )
| Número de pieza | EDS2532EESL-75 | |
| Descripción | 256M bits SDRAM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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DATA SHEET
www.DataSheet4U.com
256M bits SDRAM
EDS2532EESL-75 (8M words × 32 bits)
Specifications
• Density: 256M bits
• Organization
2M words × 32 bits × 4 banks
• Package: 92-ball FBGA
Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Clock frequency: 133MHz (max.)
• 2KB page size
Row address: A0 to A11
Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
access
• Driver strength: half/quarter
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
• Operating ambient temperature range
TA = 0°C to +70°C
Features
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
Pin Configurations
/xxx indicates active low signal.
92-ball FBGA
1 2 3 4 5 6 7 8 9 10 11
A
NC VDD VSS
B
VSSQ DQ15
C
VDDQ DQ13 DQ14
D
DQ11 DQ12
E
DQ9 DQ10 VSSQ
F
DQ8 VDDQ
G
CLK DQM1 VSS
H
CKE /CS
J
A8 NC A9
K
NC A6 A7
L
A5 A4
M
A3 DQM3 VSS
N
DQ31 VDDQ
P
DQ30 DQ29 VSSQ
R
DQ28 DQ27
S
VDDQ DQ26 DQ25
T
VSSQ DQ24
U
NC VDD VSS
(Top view)
VSS VDD NC
DQ0 VDDQ
DQ1 DQ2 VSSQ
DQ3 DQ4
VDDQ DQ5 DQ6
VSSQ DQ7
VDD DQM0 /WE
/CAS /RAS
BA0 A11 NC
A10 BA1 NC
A1 A0
VDD DQM2 A2
VSSQ DQ16
VDDQ DQ18 DQ17
DQ20 DQ19
DQ22 DQ21 VSSQ
DQ23 VDDQ
VSS VDD NC
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0888E10 (Ver. 1.0) This product became EOL in September, 2007.
Date Published March 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006
1 page  
EDS2532EESL-75
www.DataSheet4U.com
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol Grade max.
Unit Test condition
Notes
Operating current
IDD1
Standby current in power down
IDD2P
Standby current in power down
(input signal stable)
IDD2PS
Standby current in non power down
IDD2N
Standby current in non power down
(input signal stable)
IDD2NS
Active standby current in power down
IDD3P
Active standby current in power down
(input signal stable)
IDD3PS
Active standby current in non power down IDD3N
Active standby current in non power down
(input signal stable)
IDD3NS
Burst operating current
IDD4
Refresh current
Self refresh current
IDD5
IDD6
Burst length = 1
80 mA tRC = tRC (min.)
1, 2, 3
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
CKE ≤ 0.3V,
3 mA tCK = tCK (min.)
6
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
2
mA
CKE ≤ 0.3V, tCK = ∞
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
7
CKE, /CS = VIH,
20 mA tCK = tCK (min.)
4
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
9
mA
CKE = VIH, tCK = ∞,
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
8
CKE ≤ VIL,
4 mA tCK = tCK (min.)
1, 2, 6
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
3
mA
CKE ≤ VIL, tCK = ∞
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
2, 7
CKE, /CS = VIH,
20 mA tCK = tCK (min.)
1, 2, 4
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
15
mA
CKE = VIH, tCK = ∞,
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
2, 8
tCK = tCK (min.),
90 mA BL = 4
1, 2, 5
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
180
mA
tRC = tRC (min.)
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
3
3 mA VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0888E10 (Ver. 1.0)
5
5 Page 
DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
EDS2532EESL-75
www.DataSheet4U.com
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0888E10 (Ver. 1.0)
11
11 Page | ||
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