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PDF K9MDG08U5M Data sheet ( Hoja de datos )

Número de pieza K9MDG08U5M
Descripción FLASH MEMORY
Fabricantes Samsung Electronics 
Logotipo Samsung Electronics Logotipo



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No Preview Available ! K9MDG08U5M Hoja de datos, Descripción, Manual

K9MDG08U5M
K9LBG08U0M K9HCG08U1M
Preliminarywww.DataSheet4U.com
FLASH MEMORY
K9XXG08UXM
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1

1 page




K9MDG08U5M pdf
K9MDG08U5M
K9LBG08U0M K9HCG08U1M
Preliminarywww.DataSheet4U.com
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9HCG08U1M-PCB0/PIB0
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
48 N.C
47 N.C
46 N.C
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 N.C
38 N.C
37 Vcc
36 Vss
35 N.C
34 N.C
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 N.C
26 N.C
25 N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1 #48
#24
0~8°
0.45~0.75
0.018~0.030
18.40±0.10
0.724±0.004
#25
1.00±0.05
0.039±0.002
01..02407MAX
0.02
0.002
MIN
(
0.50
0.020
)
5

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K9MDG08U5M arduino
K9MDG08U5M
K9LBG08U0M K9HCG08U1M
Preliminarywww.DataSheet4U.com
FLASH MEMORY
Product Introduction
The K9LBG08U0M is a 33,792Mbit(35,433,480,192 bit) memory organized as 1,048,576 rows(pages) by 4,224x8 columns. Spare
128 columns are located from column address of 4,096~4,223. A 4,224-byte data register is connected to memory cell arrays for
accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The mem-
ory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page.
A block consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 2,162,688 NAND
cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a
block basis. The memory array consists of 4,096 separately erasable 512K-byte blocks. It indicates that the bit by bit erase operation
is prohibited on the K9LBG08U0M.
The K9LBG08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 2112M-byte physical space
requires 33 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-
ation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the com-
mand register. Table 1 defines the specific commands of the K9LBG08U0M.
Table 1. Command Sets
Function
Read
Read for Copy Back
Read ID
Reset
Page Program
Copy-Back Program
Block Erase
Random Data Input(1)
Random Data Output(1)
Read Status
Chip1 Status
Chip2 Status
Two-Plane Read (3)
Two-Plane Read for Copy-Back
Two-Plane Random Data Output (1) (3)
Two-Plane Page Program(2)
Two-Plane Copy-Back Program(2)
Two-Plane Block Erase
Page Program with 2KB Data (2)
Copy-Back Program with 2KB Data (2)
1st Set
00h
00h
90h
FFh
80h
85h
60h
85h
05h
70h
F1h
F2h
60h----60h
60h----60h
00h----05h
80h----11h
85h----11h
60h----60h
80h----11h
85h----11h
2nd Set
30h
35h
-
-
10h
10h
D0h
-
E0h
30h
35h
E0h
81h----10h
81h----10h
D0h
80h----10h
85h----10h
Acceptable Command during Busy
O
O
O
O
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h//F2h and FFh.
3. Two-Plane Random Data msut be used after Two-Plane Read operation
4. Interleave-operation between two chips is allowed.
It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
11

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